Abstract
System-on-chip (soc) design gets increasingly complex, as a growing number of applications are integrated in modern systems. Some of these applications have real-time requirements, such as a minimum throughput or a maximum latency. To reduce cost, system resources are shared between applications, making their timing behavior inter-dependent. Real-time requirements must hence be verified for all possible combinations of concurrently executing applications, which is not feasible with commonly used simulation-based techniques. This chapter addresses this problem using two complexity-reducing concepts: composability and predictability. Applications in a composable system are completely isolated and cannot affect each other’s behaviors, enabling them to be independently verified. Predictable systems, on the other hand, provide lower bounds on performance, allowing applications to be verified using formal performance analysis. Five techniques to achieve composability and/or predictability in soc resources are presented and we explain their implementation for processors, interconnect, and memories in our platform.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
B. Akesson, K. Goossens, and M. Ringhofer. Predator: a predictable SDRAM memory controller. In CODES+ISSS ’07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 251–256, 2007.
B. Akesson, A. Hansson, and K. Goossens. Composable resource sharing based on latency-rate servers. In 12th Euromicro Conference on Digital System Design (DSD), 2009.
B. Akesson, W. Hayes, and K. Goossens. Classification and Analysis of Predictable Memory Patterns. In Int’l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2010.
B. Akesson, L. Steffens, and K. Goossens. Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration. In Int’l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2009.
B. Akesson, L. Steffens, E. Strooisma, and K. Goossens. Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration. In Int’l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2008.
ARM Limited. AMBA AXI Protocol Specification, 2003.
S. Bayliss and G. Constantinides. Methodology for designing statically scheduled application-specific sdram controllers using constrained local search. In Field-Programmable Technology, 2009. International Conference on, pages 304 –307, Dec. 2009.
M. Bekooij, A. Moonen, and J. van Meerbergen. Predictable and Composable Multiprocessor System Design: A Constructive Approach. In Bits&Chips Symposium on Embedded Systems and Software, 2007.
R. Cruz. A calculus for network delay. I. Network elements in isolation. IEEE Transactions on Information Theory, 37(1):114–131, 1991.
M. Ekerhult. Compose: Design and implementation of a composable and slack-aware operating system targeting a multi-processor system-on-chip in the signal processing domain. Master’s thesis, Lund University, July 2008.
K. Goossens, J. Dielissen, and A. Rădulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5):414–421, 2005.
K. Goossens and A. Hansson. The aethereal network on chip after ten years: goals, evolution, lessons, and future. In DAC ’10: Proceedings of the 47th Design Automation Conference, pages 306–311, 2010.
K. Goossens, D. She, A. Milutinovic, and A. Molnos. Composable dynamic voltage and frequency scaling and power management for dataflow applications. In 13th Euromicro Conference on Digital System Design (DSD), Sept. 2010.
P. Gumming. The TI OMAP Platform Approach to SoC. Winning the SoC revolution: experiences in real design, page 97, 2003.
A. Hansson, M. Coenen, and K. Goossens. Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), pages 954–959, 2007.
A. Hansson and K. Goossens. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. In CODES+ISSS ’09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pages 99–108, 2009.
A. Hansson, K. Goossens, M. Bekooij, and J. Huisken. CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM Transactions on Design Automation of Electronic Systems, 14(1):1–24, 2009.
A. Hansson, M. Subbaraman, and K. Goossens. aelite: A flit-synchronous network on chip with composable and predictable services. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), Apr. 2009.
A. Hansson, M. Wiggers, A. Moonen, K. Goossens, and M. Bekooij. Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers & Digital Techniques, 2009.
S. Heithecker and R. Ernst. Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. In DAC ’05: Proceedings of the 42nd annual conference on Design automation, pages 575–578, 2005.
E. Ipek, O. Mutlu, J. Martinez, and R. Caruana. Self-optimizing memory controllers: A reinforcement learning approach. In Computer Architecture. ISCA ’08. 35th International Symposium on, pages 39–50, 2008.
International Technology Roadmap for Semiconductors (ITRS), 2009.
H. Kopetz and G. Bauer. The time-triggered architecture. Proceedings of the IEEE, 91(1):112–126, 2003.
H. Kopetz, C. El Salloum, B. Huber, R. Obermaisser, and C. Paukovits. Composability in the time-triggered system-on-chip architecture. In SOC Conference, IEEE International, pages 87–90, 2008.
E. A. Lee. Absolutely positively on time: what would it take? IEEE Transactions on Computers, 38(7):85–87, 2005.
K. Lee, T. Lin, and C. Jen. An efficient quality-aware memory controller for multimedia platform SoC. IEEE Transactions on Circuits and Systems for Video Technology, 15(5):620–633, 2005.
A. Molnos and K. Goossens. Conservative dynamic energy management for real-time dataflow applications mapped on multiple processors. In 12th Euromicro Conference on Digital System Design (DSD), 2009.
O. Moreira, F. Valente, and M. Bekooij. Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor. In EMSOFT ’07: Proceedings of the 7th ACM & IEEE international conference on Embedded software, pages 57–66, 2007.
O. Mutlu and T. Moscibroda. Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers. IEEE Micro, 29(1):22–32, 2009.
J. Muttersbach, T. Villiger, and W. Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 52–59, 2000.
A. Nieuwland, J. Kang, O. Gangwal, R. Sethuraman, N. Busá, K. Goossens, R. Peset Llopis, and P. Lippens. C-HEAP: A heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems. Design Automation for Embedded Systems, 7(3):233–270, 2002.
OCP International Partnership. Open Core Protocol Specification, 2001.
Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification. Version 2.2, 2002.
R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, and A. Ivanov. System-on-chip: Reuse and integration. Proceedings of the IEEE, 94(6):1050–1069, 2006.
J. Shao and B. Davis. A burst scheduling access reordering mechanism. In Proceedings of the 13th International Symposium on High-Performance Computer Architecture, pages 285–294, 2007.
S. Sriram and S. Bhattacharyya. Embedded multiprocessors: Scheduling and synchronization. CRC, 2000.
L. Steffens, M. Agarwal, and P. van der Wolf. Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach. ECRTS ’08: Proceedings of the Euromicro Conference on Real-Time Systems, pages 255–265, 2008.
C. van Berkel. Multi-core for Mobile Phones. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2009.
S. Verdoolaege, H. Nikolov, and T. Stefanov. PN: a tool for improved derivation of process networks. EURASIP J. Embedded Syst., 2007, 2007.
R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(7):966–978, 2009.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Akesson, B., Molnos, A., Hansson, A., Angelo, J.A., Goossens, K. (2011). Composability and Predictability for Independent Application Development,Verification, and Execution. In: Hübner, M., Becker, J. (eds) Multiprocessor System-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6460-1_2
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6460-1_2
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-6459-5
Online ISBN: 978-1-4419-6460-1
eBook Packages: EngineeringEngineering (R0)