Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA | SpringerLink
Skip to main content
Springer Nature Link
Log in

Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications (FPL 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

Included in the following conference series:

Abstract

In this paper, classical adder architectures applied to Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, a hybrid solution is proposed such that the optimal trade-off between architectures and technology is reached. The resulting scheme yields optimized performance after the use of Xilinx place and route tools.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. J. Sklansky, Conditional-Sum Addition Logic, ME Transactions on Electronic Computers, Vol. EC-9, No.2, pp. 226–231, June 1960.

    Google Scholar 

  2. R.T. Brent and H. Kung, A Regular Layout for Parallel Adders. IEEE Transactions on Computers, Vol. C-31, No.3, pp. 260–264, March 1982.

    Google Scholar 

  3. P.M. Kogge and H.S. Stone. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations, IEEE Transactions on Computers, Vol. C22, No.8, pp. 786–792, August 1973.

    Google Scholar 

  4. T.Han and D.A.Carlson, fast Area-Efficient VLSI Adders, 8th Symposium on Computer Arithmetic, pp. 49–56. May 1987.

    Google Scholar 

  5. The Programmable Logic Data Book, Xilinx 1996.

    Google Scholar 

  6. A. Guyot, M. Belrhiti, G. Bosco, Adders synthesis, IMP Workshop on logic and architecture synthesis, pp. 107–117, December 1994.

    Google Scholar 

  7. A. Bosco, M. Belrhiti, B. Laurent, Adder Solution Space Exploration for Speed/ Area Trade-offs, IFIP Workshop on logic and architecture synthesis, December 1996.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institut National Polytechnique de Grenoble/CSI, 46 Avenue Felix Viallet, 38031, Grenoble cedex, France

    B. Laurent, G. Bosco & G. Saucier

Authors
  1. B. Laurent
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. Bosco
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. G. Saucier
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Wayne Luk Peter Y. K. Cheung Manfred Glesner

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Laurent, B., Bosco, G., Saucier, G. (1997). Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_252

Download citation

  • DOI: https://doi.org/10.1007/3-540-63465-7_252

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation