Instruction-Level Parallelism and Uniprocessor Architecture

Abstract

Research in Instruction-Level Parallelism (ILP) is concerned with architectural innovations in the processor to expose parallelism between the execution of instructions. Of course, the relationship with the research on the memory hierarchy and on compiler optimisation techniques is very strong. Another point is that such a research needs tools to simulate the mechanisms. Thus, researchers have to develop their tools. Such a tool is detailed in the paper on code cloning tracing by Lafage et al from IRISA.

Most of these topics are represented in this workshop although there are no papers on the lower levels of the memory hierarchy.

The memory hierarchy, and particularly, the first-level cache is highly related to ILP research since superscalar processors place higher demands on it for obtaining more instructions and more data per cycle. In addition to the requirement of higher bandwidths, latency is also an important issue. One way to reduce the latency is prefetching as proposed by Chi and Yuan. Another issue is the way the cache is managed. Software can afford hints for a better management, which might result in a good speedup as in the paper of Lebeck et al.

A big and old deal is what should be in the hardware and what should be left in the compiler. Returning to simpler processors while leaving part of the job to the compiler might arrive in the future. Thus, we should care of compiler studies. Moreover, compiler studies might have an impact on the architecture. The papers by Norris, Fenwick and Genius, Lelait concern compiler optimisations. The first one deals with register allocation that can have a great impact on the reordering of instructions while the second one apply techniques of register allocation to the data in memory in order to improve the use of the cache. The VLIW architecture highly depends on the quality of the compiler. The paper of Ebcioglu et al gives encouraging results for such an approach.

Increasing the ILP is, at last, limited by data dependencies.

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