Abstract
General transport layer protocols like TCP/IP are relatively complex because they have to deal with very different and dynamic application requirements and networking conditions. In this paper, we present an approach for hardware support of such protocols using FPGAs. We outline a hardware/software partitioning, a heterogeneous protocol engine for protocol processing acceleration and describe its transparent integration into standard systems. For the design, development and verification of such communication systems extensive simulation support is required.We describe how protocol engine VHDL models, a network simulator and existing networking applications were integrated to support this process. For this to be accomplished, object oriented techniques were applied. We present our approach for the simulation of communication systems and discuss the object structure and implementation details. As a result, the simulation enables to evaluate different configurations, modifications or the influence of system dynamics like network transmission errors on protocol processing and achievable performance.
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Hatnik, U.; Haufe, J.; Schwarz, P.: An innovative approach to couple EDA tools with reconfigurable hardware. 10th International Conference on Field Programmable Logic and Applications, FPL, Villach (Austria), 28.-30. Aug. 2000, 826–829
Haufe, J.; Schwarz, P.; Berndt, T.; Große, J.: Accelerated Logic Simulation by Using Prototype Boards. Design, Automation and Test in Europe DATE 1998, Paris, 23.-26.2.98, 183–189 (Designer Track)
Hatnik, U.; Haufe, J.; Schwarz, P.: Object Oriented System Simulation of Large Heterogeneous Communication Systems. Workshop on System Design Automation SDA 2000, Rathen, March 13-14, 2000, 178–184
Benz, M.: The Protocol Engine Project-An Integrated Hardware / Software Architecture for Protocol Processing Acceleration, SDA 2000-Workshop on System Design Automation, Rathen, March 2000, pp. 137–144
Benz, M., Feske, K.: A Packet Classification and Validation Unit for Hardware Supported TCP/IP Receive Path Processing, SDA 2000-Workshop on System Design Automation, Rathen, March 2000, pp. 145–151
Benz, M.: An Architecture and Prototype Implementation for TCP/IP Hardware Support, accepted for publication, TERENA Networking Conference, 2001
Strayer, W.T.; Dempsey, B.J.; Weaver, A.C.: “XTP-The Xpress Transfer Protocol”, ADDISON-WESLEY, 1992
K. Fall, K. Varadhan: “Notes and Documentation”, January 2000, http://www.isi.edu/nsnam/ns/
Free High Performance CORBA 2 ORB from AT&T Laboratories Cambridge http://www.uk.research.att.com/omniORB/
European Space Agency, LEON-1 processor, http://www.estec.esa.nl/wsmwww/leon/, 2000
Virtual Interface Architecture, specification version 1.0, http://www.viarch.org, 1999
SYNOPSYS: “V1998.08 Protocol Compiler User’s Guide”, Synopsys Inc., 1998
ARM: AMBA-Advanced Microcontroller Bus Architecture, Rev2.0, http://www.arm.com, 1999
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© 2001 Springer-Verlag Berlin Heidelberg
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Benz, M., Feske, K., Hatnik, U., Schwarz, P. (2001). TCP/IP Protocol Engine System Simulation. In: van Sinderen, M.J., Nieuwenhuis, L.J.M. (eds) Protocols for Multimedia Systems. PROMS 2001. Lecture Notes in Computer Science, vol 2213. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45481-0_13
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DOI: https://doi.org/10.1007/3-540-45481-0_13
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