Abstract
Simultaneous multithreading (SMT) processors achieve high performance by executing independent instructions from different programs simultaneously [1]. However, the SMT model doesn’t help single-thread applications and performs at its full potential only when executing multithreaded applications or multiple programs. Moreover, to minimize the total execution time of one selected high priority thread, that thread has to run alone. Recently, several speculative multithreading architectures have been proposed that exploit far away instruction level parallelism in single-thread applications. In particular, the dynamic multithreading or DMT model [2] uses hardware mechanisms to fork speculative threads at procedure and loop boundaries along the execution path of a single program, and executes these threads on a multithreaded processor. In this paper, we explore the performance scope of an SMT architecture in which spare thread contexts are used to support the DMT execution of procedure and loop threads. We show two significant advantages of this approach: (1) it increases processor utilization and total execution throughput when few programs are running, and (2) it eliminates or reduces the performance degradation of one selected high priority program when running simultaneously with other programs, without reducing total SMT throughput.
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Akkary, H., Hily, S. (2000). The Case for Speculative Multithreading on SMT Processors. In: Valero, M., Joe, K., Kitsuregawa, M., Tanaka, H. (eds) High Performance Computing. ISHPC 2000. Lecture Notes in Computer Science, vol 1940. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39999-2_7
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DOI: https://doi.org/10.1007/3-540-39999-2_7
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