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A Heterogeneous Multi-core Processor Architecture for High Performance Computing

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Advances in Computer Systems Architecture (ACSAC 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4186))

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Abstract

The increasing application demands put great pressure on high performance processor design. This paper presents a multi-core System-on-Chip architecture for high performance computing. It is composed of a sparcv8-compliant LEON3 host processor and a data parallel coprocessor based on transport triggered architecture, all of which are tied with a 32-bit AMBA AHB bus. The LEON3 processor performs control tasks and the data parallel coprocessor performs computing intensive tasks. The chip is fabricated in 0.18um standard-cell technology, occupies about 5.3mm2 and runs at 266MHz.

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Author information

Authors and Affiliations

  1. School of Computer, National University of Defense Technology, 410073, Changsha, Hunan, China

    Jianjun Guo, Kui Dai & Zhiying Wang

Authors
  1. Jianjun Guo
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  2. Kui Dai
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  3. Zhiying Wang
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Editor information

Editors and Affiliations

  1. Computer Systems Architecture Group, University of Amsterdam, The Netherlands

    Chris Jesshope

  2. School of Computer Science, University of Hertfordshire, College Lane, AL10 9AB, Hatfield, UK

    Colin Egan

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© 2006 Springer-Verlag Berlin Heidelberg

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Guo, J., Dai, K., Wang, Z. (2006). A Heterogeneous Multi-core Processor Architecture for High Performance Computing. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_30

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  • DOI: https://doi.org/10.1007/11859802_30

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40056-1

  • Online ISBN: 978-3-540-40058-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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