On the Effects of Errors During Boot | SpringerLink
Skip to main content

On the Effects of Errors During Boot

  • Conference paper
Dependable Computing (LADC 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3747))

Included in the following conference series:

  • 329 Accesses

Abstract

We present the results of injecting errors during the boot phase of an embedded real-time system based on the ERC32 space processor. In this phase the hardware is initialized, and the processor executes the boot loader followed by kernel initialization. For this reason most system support is not yet available and traditional fault-injection techniques such as swifi cannot be used. Thus our study was based in the processor’s IEEE 1149.1 (boundary-scan) infrastructure through which we injected about 5000 double bit-flip errors. The observations show that such system will either crash(25%) or execute correctly(75%), since only 2 errors eventually lead to the output of wrong results. However about 10% of faults originated latent errors dormant in memory. We also provide some suggestions on what can be done to increase robustness during this system state, in which most fault-tolerance techniques are not yet setup.

This work was partially supported by the R&D Unit 326/94 (Center for Informatics and Systems, CISUC), and the Portuguese Agency for Innovation (AdI) through project BSCAN4FI.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Cunha, J., Correia, A., Henriques, J., Rela, M.Z., Silva, J.: Reset-Driven Fault Tolerance. In: Bondavalli, A., Thévenod-Fosse, P. (eds.) EDCC 2002. LNCS, vol. 2485, pp. 102–120. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  2. Laprie, J.-C., Avižienis, A., Kopetz, H. (eds.): Dependability: Basic Concepts and Terminology, p. 268. Springer, Heidelberg (1992) ISBN:0-3878229-6-8

    MATH  Google Scholar 

  3. Potteck, S.: La conception de systèmes spatiaux, Éditions du Schèmectif, Juillet (2 Tomes) (2001) ISBN 2-9513724-0-X

    Google Scholar 

  4. IEEE Std 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture, New York (2001) ISBN: 0738129445

    Google Scholar 

  5. Folkesson, P., Svensson, S., Karlsson, J.: A comparison of simulation based and scan chain implemented fault injection. In: Proc. of 28th Symposium on Fault Tolerant Computer Systems (FTCS-28), Munich, Germany, pp. 284–293. IEEE Computer Society, Los Alamitos (1998)

    Google Scholar 

  6. Santos, L., Rela, M.Z.: Constraints on the use of boundary-scan for fault injection. In: de Lemos, R., Weber, T.S., Camargo Jr., J.B. (eds.) LADC 2003. LNCS, vol. 2847, pp. 39–55. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  7. TSC695 Evaluation Board User Guide Manual, Rev.C 01/00, ATMEL Corp /microelectronics (2000), http://www.estec.esa.nl/presentation/ERC32.pdf

  8. RTEMS: Real-Time Executive for Multiprocessor Systems., http://www.rtems.com/

  9. http://www.estec.esa.nl/wsmwww/erc32/freesoft.html

  10. Gaisler, J.: Evaluation of a 32-bit Microprocessor with Built-In Concurrent Error-Detection. In: Proc. FTCS-27, June 25-27, pp. 42–46. IEEE Computer Society, Los Alamitos (1997)

    Google Scholar 

  11. Yuste, P., Ruiz, J.-C., Lemus, L., Gil, P.: Non-intrusive Software-Implemented Fault Injection in Embedded Systems. In: de Lemos, R., Weber, T.S., Camargo Jr., J.B. (eds.) LADC 2003. LNCS, vol. 2847, pp. 23–38. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  12. XceptionT M-Enhanced Automated Fault-Injection Environment (2002), http://www.xception.org

  13. Carreira, J., Madeira, H., Silva, J.G.: Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers. IEEE Trans. on Software Engineering (February 1998)

    Google Scholar 

  14. Madeira, H., Silva, J.G.: Experimental Evaluation of the Fail-silent behaviour in Computers without Error Masking. In: Proc. FTCS-24, Austin-USA, pp. 350–359. IEEE Computer Society, Los Alamitos (1994)

    Google Scholar 

  15. Cunha, J., Maia, R., Rela, M.Z., Silva, J.G.: A Study of Failure Models in Feedback Control Systems. In: Proc. DSN 2001, Göteborg-Sweden, July 1-4, IEEE Computer Society, Los Alamitos (2001)

    Google Scholar 

  16. Iyer, R.K., Tang, D.: Experimental Analysis of Computer System Dependability. In: Pradhan, D.K. (ed.) Chap. 5 in Fault-Tolerant Computer System Design, pp. 282–392. Prentice Hall, Englewood Cliffs (1996) ISBN 0-13-057887-8

    Google Scholar 

  17. Powell, D., Bonn, G., Seaton, D., Verissimo, P., et al.: The Delta-4 approach to dependability in open distributed computing systems. In: Proc. FTCS 18, Japan (June 1988)

    Google Scholar 

  18. Vinter, J., Johansson, A., Folkesson, P., Karlsson, J.: On the Design of Robust Integrators for Fail-Bounded Control Systems. In: DSN 2003, pp. 415–424. IEEE Computer Society, Los Alamitos (2003) ISBN 0-7695-1952-0

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Zenha-Rela, M., Cunha, J.C., Silva, C.B., da Silva, L.F. (2005). On the Effects of Errors During Boot. In: Maziero, C.A., Gabriel Silva, J., Andrade, A.M.S., de Assis Silva, F.M. (eds) Dependable Computing. LADC 2005. Lecture Notes in Computer Science, vol 3747. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572329_12

Download citation

  • DOI: https://doi.org/10.1007/11572329_12

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29572-3

  • Online ISBN: 978-3-540-32092-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics