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Improved Blocks for CMOS Analog Neuro-fuzzy Network

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Advances in Natural Computation (ICNC 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3612))

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Abstract

This paper proposes several improved CMOS analog circuits for neuro-fuzzy network, including Gaussian-like membership function circuit, minimization circuit, and a centroid algorithm defuzzier circuit without using division. A two-input/one-output neuro-fuzzy network composed of these circuits is implemented and testified for non-linear function approximating. HSPICE simulation results show that all the proposed circuits provide characteristics of high operation capacity, high speed, simple structures, and high precision. They are very suitable for rapid implementation of neuro-fuzzy networks.

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Author information

Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, 100084, Beijing, China

    Weizhi Wang & Dongming Jin

Authors
  1. Weizhi Wang
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  2. Dongming Jin
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Editors and Affiliations

  1. School of Electrical and Electronic Engineering, Nanyang Technological University, Block S1, Nanyang Avenue, 639798, Singapore

    Lipo Wang

  2. School of Software, Sun Yat-Sen University, 510275, Guangzhou, China

    Ke Chen

  3. School of Computer Engineering, Nanyang Technological University, BLK N4, 2b-39, Nanyang Avenue, 639798, Singapore

    Yew Soon Ong

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© 2005 Springer-Verlag Berlin Heidelberg

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Wang, W., Jin, D. (2005). Improved Blocks for CMOS Analog Neuro-fuzzy Network. In: Wang, L., Chen, K., Ong, Y.S. (eds) Advances in Natural Computation. ICNC 2005. Lecture Notes in Computer Science, vol 3612. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11539902_131

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  • DOI: https://doi.org/10.1007/11539902_131

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-28320-1

  • Online ISBN: 978-3-540-31863-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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