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Flux Caches: What Are They and Are They Useful?

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Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3553))

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Abstract

In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to the traditional approaches, processors designed with flux caches instead of assuming a hardwired cache organization change their cache ”design” on program demand. Consequently program (data and instruction) dynamic behavior determines the cache hardware design. Experimental results to confirm the flux caches potential are also presented.

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References

  1. Dejuan, E., Casals, O., Labarta, J.: Cache memory with hybrid mapping. In: 7th International Conference on Modelling, Identification and Control, Grindelwald, pp. 27–30 (1987)

    Google Scholar 

  2. Dejuan, E., Casals, O., Labarta, J.: Management algorithms for an hybrid mapping cache memory. In: International Conference on Mini an Microcomputers and their applications, Sant Feliu, pp. 368–372 (1988)

    Google Scholar 

  3. Jouppi, N.P.: Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In: ISCA, pp. 364–373 (1990)

    Google Scholar 

  4. Agarwal, A., Pudar, S.D.: Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. In: ISCA, pp. 179–190 (1993)

    Google Scholar 

  5. Seznec, A.: A case for two-way skewed-associative caches. In: ISCA, pp. 169–178 (1993)

    Google Scholar 

  6. Chan, K.K., Hay, C.C., Keller, J.R., Kurpanek, G.P., Schumacher, F.X., Zheng, J.: Design of the HP PA 7200 CPU processor chip. Hewlett-Packard Journal 47, 25–33 (1996)

    Google Scholar 

  7. Milutinovic, V., Markovic, B., Tomasevic, M., Tremblay, M.: The split temporal/spatial cache: Initial performance analysis. In: Proceedings of SCIzzL, vol. 5, pp. 63–69 (1996)

    Google Scholar 

  8. Sánchez, F.J., González, A., Valero, M.: Software management of selective and dual data caches. In: Technical Committee on Computer Architecture (TCCA) Newsletter (1997)

    Google Scholar 

  9. Ranganathan, P., Adve, S.V., Jouppi, N.P.: Reconfigurable caches and their application to media processing. In: ISCA, pp. 214–224 (2000)

    Google Scholar 

  10. Zhang, C., Vahid, F., Najjar, W.A.: Energy benefits of a configurable line size cache for embedded systems. In: ISVLSI, pp. 87–91 (2003)

    Google Scholar 

  11. Hartenstein, R.W., Kress, R., Reining, H.: A new FPGA Architecture for Word-Oriented Datapaths. In: 4th International Workshop on Field Programmable Logic and Applications: Architectures, Synthesis and Applications, pp. 144–155 (1994)

    Google Scholar 

  12. Trimberger, S.M.: Reprogramable Instruction Set Accelerator. U.S. Patent No. 5 737, 631 (1998)

    Google Scholar 

  13. Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN ρμ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  14. Gordon-Ross, A., Vahid, F., Dutt, N.: Automatic tuning of two-level caches to embedded applications. In: DATE, pp. 208–213 (2004)

    Google Scholar 

  15. Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G., Panainte, E.M.: The molen polymorphic processor. IEEE Transactions on Computers, 1363–1375 (2004)

    Google Scholar 

  16. Vassiliadis, S., Gaydadjiev, G.N., Bertels, K., Panainte, E.M.: The molen programming paradigm. In: Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp. 1–10 (2003)

    Google Scholar 

  17. Kurpanek, G., Chan, K., Zheng, J., DeLano, E., Bryg, W.: Pa7200: A pa-risc processor with integrated high performance mp bus interface. In: COMPCON, pp. 375–382 (1994)

    Google Scholar 

  18. Veidenbaum, A.V., Tang, W., Gupta, R., Nicolau, A., Ji, X.: Adapting cache line size to application behavior. In: ICS 1999: Proceedings of the 13th international conference on Supercomputing, New York, NY, USA, pp. 145–154. ACM Press, New York (1999)

    Chapter  Google Scholar 

  19. Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: Visual data rectangular memory. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds.) Euro-Par 2004. LNCS, vol. 3149, pp. 760–767. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  20. Edler, J., Hill, M.D.: Dinero IV trace-driven uniprocessor cache simulator (1998), http://www.cs.wisc.edu/~markhill/DineroIV

  21. Smith, A.: Cache Memories. Computing Surveys 14, 473–530 (1982)

    Article  Google Scholar 

  22. Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308 (1996)

    Google Scholar 

  23. Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In: 30th Annual International Symposium on Microarchitecture, MICRO30, pp. 330–335 (1997)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Computer Engineering, EEMCS, TU Delft, The Netherlands

    Georgi N. Gaydadjiev & Stamatis Vassiliadis

Authors
  1. Georgi N. Gaydadjiev
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  2. Stamatis Vassiliadis
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Editor information

Editors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 553, FI-33101, Tampere, Finland

    Timo D. Hämäläinen

  2. Computer Systems Architecture Group, University of Amsterdam, The Netherlands

    Andy D. Pimentel

  3. Tampere University of Technology, Korkeakoulunkatu 1, 33720, Tampere, Finland

    Jarmo Takala

  4. Computer Engineering Lab, TUDelft., Postbus 5031, 2600, Delft, GA, The Netherlands

    Stamatis Vassiliadis

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© 2005 Springer-Verlag Berlin Heidelberg

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Gaydadjiev, G.N., Vassiliadis, S. (2005). Flux Caches: What Are They and Are They Useful?. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_11

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  • DOI: https://doi.org/10.1007/11512622_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-26969-4

  • Online ISBN: 978-3-540-31664-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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