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ORCIDHai Zhou 0001
Person information
- affiliation: Northwestern University, Evanston, IL, USA
- affiliation: ICBench Inc., Shanghai, China
Other persons with the same name
- Hai Zhou — disambiguation page
- Hai Zhou 0002
![[0000-0002-0869-3038]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-0869-3038")
— Huazhong University of Science and Technology, Wuhan National Laboratory for Optoelectronics, Wuhan, Hubei, China
Other persons with a similar name
- Hai Zhou Chen
- Hai-zhou Gao
- Hai Zhou Ling
- Bing-Hai Zhou (aka: Binghai Zhou, Bing-hai Zhou) — disambiguation page
- Hai-Jun Zhou
- Hai-Yan Zhou
- Hai-Yang Zhou
- Hai-jing Zhou
- Hai Sen Zhou
- Song-hai Zhou
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2020 – today
- 2024
[j56]Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 810-822 (2024)- [c130]You Li, Guannan Zhao, Yunqi He, Hai Zhou:
Evaluating the Security of Logic Locking on Deep Neural Networks. DAC 2024: 286:1-286:6 - [c129]You Li, Kaiyu Hou, Yunqi He, Yan Chen, Hai Zhou:
Property Guided Secure Configuration Space Search. ISC (2) 2024: 140-160 - [i18]You Li, Guannan Zhao, Shuyu Kong, Yunqi He, Hai Zhou:
Certifying Global Robustness for Deep Neural Networks. CoRR abs/2405.20556 (2024) - 2023
- [j55]Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. 28(2): 21:1-21:24 (2023) - [j54]Igor L. Markov, Fan Yang, Li Shang, Hai Zhou:
Guest Editor's Introduction: Machine Learning for VLSI Physical Design. ACM Trans. Design Autom. Electr. Syst. 28(4): 48:1-48:3 (2023) - [c128]You Li, Guannan Zhao, Yunqi He, Hai Zhou:
SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †. DAC 2023: 1-6 - [c127]You Li, Guannan Zhao, Yunqi He, Hai Zhou:
ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection†. DATE 2023: 1-6 - [c126]Yunqi He, Linglong Cai, Taimei Cui, You Li, Hai Zhou:
A Combination of DNN and BN for Automatic Skin Disease Diagnosis. ISBI 2023: 1-5 - 2022
- [c125]Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Floorplanning with graph attention. DAC 2022: 1303-1308 - [c124]Amin Rezaei, Ava Hedayatipour, Hossein Sayadi, Mehrdad Aliasgari, Hai Zhou:
Global Attack and Remedy on IC-Specific Logic Encryption. HOST 2022: 145-148 - [i17]Shuyu Kong, You Li, Hai Zhou:
Incentivizing Federated Learning. CoRR abs/2205.10951 (2022) - 2021
- [c123]Amin Rezaei, Hai Zhou:
Sequential Logic Encryption Against Model Checking Attack. DATE 2021: 1178-1181 - [c122]Kaiyu Hou, You Li, Yinbo Yu, Yan Chen, Hai Zhou:
Discovering emergency call pitfalls for cellular networks with formal methods. MobiSys 2021: 296-309 - [i16]Amin Rezaei, Hai Zhou:
Sequential Logic Encryption Against Model Checking Attack. IACR Cryptol. ePrint Arch. 2021: 109 (2021) - [i15]Amin Rezaei, Jie Gu, Hai Zhou:
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. IACR Cryptol. ePrint Arch. 2021: 1313 (2021) - 2020
- [c121]Amin Rezaei, Yuanqi Shen, Hai Zhou:
Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation. DATE 2020: 13-18 - [c120]You Li, Kaiyu Hou, Hai Zhou, Yan Chen:
Network protocol safe configuration search in one shot. SIGCOMM Posters and Demos 2020: 21-23 - [i14]Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020) - [i13]Shuyu Kong, You Li, Jia Wang, Amin Rezaei, Hai Zhou:
KNN-enhanced Deep Learning Against Noisy Labels. CoRR abs/2012.04224 (2020)
2010 – 2019
- 2019
- [j53]Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2655-2667 (2019) - [c119]Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou:
CycSAT-unresolvable cyclic logic encryption using unreachable states. ASP-DAC 2019: 358-363 - [c118]Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou:
BeSAT: behavioral SAT-based attack on cyclic logic encryption. ASP-DAC 2019: 657-662 - [c117]Zhengyu Chen, Hai Zhou, Jie Gu:
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC 2019: 67 - [c116]Yuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, Hai Zhou:
SigAttack: New High-level SAT-based Attack on Logic Encryptions. DATE 2019: 940-943 - [c115]Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE 2019: 1040-1045 - [c114]Hai Zhou, Amin Rezaei, Yuanqi Shen:
Resolving the Trilemma in Logic Encryption. ICCAD 2019: 1-8 - [c113]Yinbo Yu, You Li, Kaiyu Hou, Yan Chen, Hai Zhou, Jianfeng Yang:
CellScope: Automatically Specifying and Verifying Cellular Network Protocols. SIGCOMM Posters and Demos 2019: 21-23 - [i12]Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou:
BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption. IACR Cryptol. ePrint Arch. 2019: 59 (2019) - [i11]Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou:
CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States. IACR Cryptol. ePrint Arch. 2019: 60 (2019) - [i10]Yuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, Hai Zhou:
SigAttack: New High-level SAT-based Attack on Logic Encryptions. IACR Cryptol. ePrint Arch. 2019: 61 (2019) - [i9]Hai Zhou, Yuanqi Shen, Amin Rezaei:
Vulnerability and Remedy of Stripped Function Logic Locking. IACR Cryptol. ePrint Arch. 2019: 139 (2019) - [i8]Hai Zhou, Amin Rezaei, Yuanqi Shen:
Resolving the Trilemma in Logic Encryption. IACR Cryptol. ePrint Arch. 2019: 918 (2019) - [i7]Amin Rezaei, Yuanqi Shen, Hai Zhou:
Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation. IACR Cryptol. ePrint Arch. 2019: 1463 (2019) - 2018
- [j52]Amin Rezaei, Masoud Daneshtalab, Hai Zhou:
Chapter Three - Multiobjectivism in Dark Silicon Age. Adv. Comput. 110: 83-126 (2018) - [j51]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng:
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. 23(3): 36:1-36:23 (2018) - [j50]Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng:
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - [j49]Shuyu Kong, Hai Zhou, Jie Gu:
Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2648-2660 (2018) - [c112]Yuanqi Shen, Amin Rezaei, Hai Zhou:
A comparative investigation of approximate attacks on logic encryptions. ASP-DAC 2018: 271-276 - [c111]Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. DATE 2018: 85-90 - [c110]Yuanqi Shen, Amin Rezaei, Hai Zhou:
SAT-based bit-flipping attack on logic encryptions. DATE 2018: 629-632 - [c109]Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD 2018: 163-170 - 2017
- [j48]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [c108]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c107]Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An efficient algorithm for stencil planning and optimization in E-beam lithography. ASP-DAC 2017: 366-371 - [c106]Yuanqi Shen, Hai Zhou:
Double DIP: Re-Evaluating Security of Logic Encryption Algorithms. ACM Great Lakes Symposium on VLSI 2017: 179-184 - [c105]Shuyu Kong, Yuanqi Shen, Hai Zhou:
Using Security Invariant To Verify Confidentiality in Hardware Design. ACM Great Lakes Symposium on VLSI 2017: 487-490 - [c104]Hai Zhou, Ruifeng Jiang, Shuyu Kong:
CycSAT: SAT-based attack on cyclic logic encryptions. ICCAD 2017: 49-56 - [c103]Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. ISPA/IUCC 2017: 814-821 - [c102]Shuyu Kong, Jie Gu, Hai Zhou:
Memristor-Based Clock Design and Optimization with In-Situ Tunability. ISVLSI 2017: 427-432 - [c101]Amin Rezaei, Dan Zhao, Masoud Daneshtalab, Hai Zhou:
Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age. PDP 2017: 589-592 - [i6]Yuanqi Shen, Hai Zhou:
Double DIP: Re-Evaluating Security of Logic Encryption Algorithms. IACR Cryptol. ePrint Arch. 2017: 290 (2017) - [i5]Hai Zhou, Ruifeng Jiang, Shuyu Kong:
CycSAT: SAT-Based Attack on Cyclic Logic Encryptions. IACR Cryptol. ePrint Arch. 2017: 626 (2017) - [i4]Hai Zhou:
A Humble Theory and Application for Logic Encryption. IACR Cryptol. ePrint Arch. 2017: 696 (2017) - [i3]Yuanqi Shen, Amin Rezaei, Hai Zhou:
A Comparative Investigation of Approximate Attacks on Logic Encryptions. IACR Cryptol. ePrint Arch. 2017: 998 (2017) - [i2]Yuanqi Shen, Amin Rezaei, Hai Zhou:
SAT-based Bit-flipping Attack on Logic Encryptions. IACR Cryptol. ePrint Arch. 2017: 1170 (2017) - [i1]Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. IACR Cryptol. ePrint Arch. 2017: 1176 (2017) - 2016
- [j47]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - 2015
- [j46]Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng:
Multi-parameter clock skew scheduling. Integr. 48: 129-137 (2015) - [j45]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - [c100]Yuankai Chen, Hai Zhou:
Synthesis of resilient circuits from guarded atomic actions. ASP-DAC 2015: 550-555 - [c99]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC 2015: 652-657 - 2014
- [j44]Xingbao Zhou, Fan Yang, Hai Zhou, Min Gong, Hengliang Zhu, Ye Zhang, Xuan Zeng:
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(11): 2227-2235 (2014) - [j43]Li Li, Yinghai Lu, Hai Zhou:
Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1888-1897 (2014) - [c98]Yuankai Chen, Xuan Zeng, Hai Zhou:
Recovery-based resilient latency-insensitive systems. DATE 2014: 1-6 - [c97]Li Li, Hai Zhou:
On error modeling and analysis of approximate adders. ICCAD 2014: 511-518 - 2013
- [j42]Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng:
Post-routing layer assignment for double patterning with timing critical paths consideration. Integr. 46(2): 153-164 (2013) - [j41]Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
An efficient method for gradient-aware dummy fill synthesis. Integr. 46(3): 301-309 (2013) - [j40]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng:
SmipRef: An efficient method for multi-domain clock skew scheduling. Integr. 46(4): 392-403 (2013) - [j39]Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun:
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 325-338 (2013) - [c96]Yuankai Chen, Hai Zhou:
Resource-constrained high-level datapath optimization in ASIP design. DATE 2013: 198-201 - [c95]Yinghai Lu, Hai Zhou:
Retiming for Soft Error Minimization Under Error-Latching Window Constraints. DATE 2013: 1008-1013 - [c94]Li Li, Hai Zhou:
Structural transformation for best-possible obfuscation of sequential circuits. HOST 2013: 55-60 - [c93]Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD 2013: 170-177 - 2012
- [c92]Yuankai Chen, Hai Zhou:
Buffer minimization in pipelined SDF scheduling on multi-core platforms. ASP-DAC 2012: 127-132 - [c91]Li Li, Yinghai Lu, Hai Zhou:
Optimal prescribed-domain clock skew scheduling. ASP-DAC 2012: 523-527 - [c90]Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu:
Clock skew scheduling for timing speculation. DATE 2012: 929-934 - [c89]Li Li, Peng Kang, Yinghai Lu, Hai Zhou:
An efficient algorithm for library-based cell-type selection in high-performance low-power designs. ICCAD 2012: 226-232 - [c88]Yinghai Lu, Hai Zhou:
Efficient design space exploration for component-based system design. ICCAD 2012: 466-472 - 2011
- [j38]Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng:
Binning Optimization for Transparently-Latched Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 270-283 (2011) - [j37]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 402-415 (2011) - [j36]Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou:
MSV-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1152-1162 (2011) - [j35]Kurt Keutzer, Peng Li, Li Shang, Hai Zhou:
A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. ACM Trans. Design Autom. Electr. Syst. 16(3): 21:1-21:2 (2011) - [j34]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 443-456 (2011) - [c87]James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng:
Parallel cross-layer optimization of high-level synthesis and physical design. ASP-DAC 2011: 467-472 - [c86]Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
Low power discrete voltage assignment under clock skew scheduling. ASP-DAC 2011: 515-520 - [c85]Yanling Zhi, Hai Zhou, Xuan Zeng:
A practical method for multi-domain clock skew optimization. ASP-DAC 2011: 521-526 - [c84]Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
Post-routing layer assignment for double patterning. ASP-DAC 2011: 793-798 - [c83]Li Li, Yinghai Lu, Hai Zhou:
Optimal multi-domain clock skew scheduling. DAC 2011: 152-157 - [c82]Yuankai Chen, Hai Zhou, Robert P. Dick:
Integrated circuit white space redistribution for temperature optimization. DATE 2011: 613-618 - [c81]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng:
An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369 - 2010
- [j33]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou:
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 466-478 (2010) - [j32]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng:
Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1546-1557 (2010) - [c80]Debasish Das, Jia Wang, Hai Zhou:
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC 2010: 61-67 - [c79]Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang:
Hybrid energy storage system integration for vehicles. ISLPED 2010: 369-374
2000 – 2009
- 2009
- [j31]Jia Wang, Debasish Das, Hai Zhou:
Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1071-1084 (2009) - [j30]Kurt Keutzer, Peng Li, Li Shang, Hai Zhou:
ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. ACM Trans. Design Autom. Electr. Syst. 15(1): 9:1-9:2 (2009) - [j29]DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail:
A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 843-847 (2009) - [c78]Jia Wang, Hai Zhou:
Exploring adjacency in floorplanning. ASP-DAC 2009: 367-372 - [c77]Jia Wang, Hai Zhou:
Risk aversion min-period retiming under process variations. ASP-DAC 2009: 480-485 - [c76]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC 2009: 636-641 - [c75]Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng:
Statistical reliability analysis under process variation and aging effects. DAC 2009: 514-519 - [c74]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Provably good and practically efficient algorithms for CMP dummy fill. DAC 2009: 539-544 - [c73]Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng:
Multicore parallel min-cost flow algorithm for CAD applications. DAC 2009: 832-837 - [c72]Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu:
Exception triggered DoS attacks on wireless networks. DSN 2009: 13-22 - [c71]Hai Zhou:
Retiming and resynthesis with sweep are complete for sequential transformation. FMCAD 2009: 192-197 - [c70]Min Gong, Hai Zhou, Jun Tao, Xuan Zeng:
Binning optimization based on SSTA for transparently-latched circuits. ICCAD 2009: 328-335 - [c69]Debasish Das, William Scott, Shahin Nazarian, Hai Zhou:
An efficient current-based logic cell model for crosstalk delay analysis. ISQED 2009: 627-633 - 2008
- [j28]Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2169-2182 (2008) - [j27]Hai Zhou:
A new efficient retiming algorithm derived by formal manipulation. ACM Trans. Design Autom. Electr. Syst. 13(1): 7:1-7:19 (2008) - [j26]Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou:
Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. 13(1): 21:1-21:13 (2008) - [j25]Ruiming Chen, Hai Zhou:
Fast Estimation of Timing Yield Bounds for Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 241-248 (2008) - [c68]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC 2008: 42-48 - [c67]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou:
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491 - [c66]Jia Wang, Hai Zhou:
An efficient incremental algorithm for min-area retiming. DAC 2008: 528-533 - [c65]Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee:
State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT 2008: 11-20 - [c64]Jia Wang, Hai Zhou:
Linear constraint graph for floorplan optimization with soft blocks. ICCAD 2008: 9-15 - [c63]Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. ISPD 2008: 126-133 - [r4]Hai Zhou:
Circuit Retiming. Encyclopedia of Algorithms 2008 - [r3]Hai Zhou:
Circuit Retiming: An Incremental Approach. Encyclopedia of Algorithms 2008 - [r2]Hai Zhou:
Rectilinear Spanning Tree. Encyclopedia of Algorithms 2008 - [r1]Hai Zhou:
Rectilinear Steiner Tree. Encyclopedia of Algorithms 2008 - 2007
- [j24]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 447-455 (2007) - [j23]Chuan Lin, Hai Zhou:
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1222-1232 (2007) - [j22]Jia Wang, Hai Zhou:
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1445-1453 (2007) - [j21]Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1522-1533 (2007) - [j20]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1576-1588 (2007) - [j19]Ruiming Chen, Hai Zhou:
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2069-2073 (2007) - [c62]Ruiming Chen, Hai Zhou:
Fast Buffer Insertion for Yield Optimization Under Process Variations. ASP-DAC 2007: 19-24 - [c61]Ruiming Chen, Hai Zhou:
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. ASP-DAC 2007: 462-467 - [c60]Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee:
Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485 - [c59]Chuan Lin, Hai Zhou:
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ASP-DAC 2007: 541-546 - [c58]Ruiming Chen, Hai Zhou:
Fast Min-Cost Buffer Insertion under Process Variations. DAC 2007: 338-343 - [c57]Chuan Lin, Aiguo Xie, Hai Zhou:
Design closure driven delay relaxation based on convex cost network flow. DATE 2007: 63-68 - [c56]Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack:
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI 2007: 25-30 - [c55]Jia Wang, Ming-Yang Kao, Hai Zhou:
Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI 2007: 525-528 - [c54]Jia Wang, Debasish Das, Hai Zhou:
Gate sizing by Lagrangian relaxation revisited. ICCAD 2007: 111-118 - [c53]Ruiming Chen, Hai Zhou:
Timing budgeting under arbitrary process variations. ICCAD 2007: 344-349 - [c52]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 - [c51]Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880 - [e2]Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud:
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. ACM 2007, ISBN 978-1-59593-605-9 [contents] - 2006
- [j18]Debjit Sinha, Hai Zhou:
Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1064-1074 (2006) - [j17]Chuan Lin, Hai Zhou:
Optimal wire retiming without binary search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1577-1588 (2006) - [j16]Ruiming Chen, Hai Zhou:
Statistical timing verification for transparently latched circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1847-1855 (2006) - [j15]Debjit Sinha, Hai Zhou:
Statistical Timing Analysis With Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2965-2975 (2006) - [j14]Ruiming Chen, Hai Zhou:
An Efficient Data Structure for Maxplus Merge in Dynamic Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3004-3009 (2006) - [j13]Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1140-1146 (2006) - [j12]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for Processing Rate Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1264-1275 (2006) - [c50]Jia Wang, Hai Zhou:
Optimal jumper insertion for antenna avoidance under ratio upper-bound. DAC 2006: 761-766 - [c49]Chuan Lin, Hai Zhou:
An efficient retiming algorithm under setup and hold constraints. DAC 2006: 945-950 - [c48]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623 - [c47]Chuan Lin, Hai Zhou, Chris C. N. Chu:
A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171 - [c46]Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou:
A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407 - [c45]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD 2006: 43-49 - [c44]Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311 - [c43]Jia Wang, Hai Zhou, Ping-Chih Wu:
Processing Rate Optimization by Sequential System Floorplanning. ISQED 2006: 340-345 - [c42]Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou:
Yield-Aware Cache Architectures. MICRO 2006: 15-25 - [e1]Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou:
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. ACM 2006, ISBN 1-59593-347-6 [contents] - 2005
- [j11]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1066-1075 (2005) - [j10]Chuan Lin, Hai Zhou:
Wire retiming as fixpoint computation. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1340-1348 (2005) - [c41]Debjit Sinha, Hai Zhou:
Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197 - [c40]Hai Zhou:
Deriving a new efficient algorithm for min-period retiming. ASP-DAC 2005: 990-993 - [c39]Jia Wang, Hai Zhou:
Interconnect estimation without packing via ACG floorplans. ASP-DAC 2005: 1152-1155 - [c38]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium 2005: 28-33 - [c37]Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207 - [c36]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Incremental exploration of the combined physical and behavioral design space. DAC 2005: 208-213 - [c35]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for processing rate optimization. ICCAD 2005: 189-195 - [c34]Ruiming Chen, Hai Zhou:
Efficient algorithms for buffer insertion in general circuits based on network flow. ICCAD 2005: 322-326 - [c33]Chuan Lin, Hai Zhou:
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ICCAD 2005: 329-334 - [c32]Debjit Sinha, Hai Zhou:
A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843 - [c31]Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041 - [c30]Min Pan, Chris C. N. Chu, Hai Zhou:
Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464 - 2004
- [j9]Hai Zhou:
Efficient Steiner tree construction based on spanning graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 704-710 (2004) - [j8]Hai Zhou, Chuan Lin:
Retiming for wire pipelining in system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1338-1345 (2004) - [c29]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690 - [c28]Chuan Lin, Hai Zhou:
Wire Retiming for System-on-Chip by Fixpoint Computation. DATE 2004: 1092-1097 - [c27]Jia Wang, Hai Zhou:
Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI 2004: 131-135 - [c26]Debjit Sinha, Hai Zhou:
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19 - [c25]Ruiming Chen, Hai Zhou:
Timing macro-modeling of IP blocks with crosstalk. ICCAD 2004: 155-159 - [c24]Chuan Lin, Hai Zhou:
Optimal wire retiming without binary search. ICCAD 2004: 452-458 - [c23]Ruiming Chen, Hai Zhou:
Clock schedule verification under process variations. ICCAD 2004: 619-625 - [c22]Ruiming Chen, Hai Zhou:
A Flexible Data Structure for Efficient Buffer Insertion. ICCD 2004: 216-221 - [c21]Hai Zhou, Jia Wang:
ACG-Adjacent Constraint Graph for General Floorplans. ICCD 2004: 572-575 - [c20]Debjit Sinha, Hai Zhou, Chris C. N. Chu:
Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181 - 2003
- [j7]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods Syst. Des. 22(3): 205-224 (2003) - [j6]Hai Zhou:
Timing analysis with crosstalk is a fixpoint on a complete lattice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1261-1269 (2003) - [c19]Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou:
Interconnect-driven floorplanning by searching alternative packings. ASP-DAC 2003: 417-422 - [c18]Hai Zhou:
Timing Verification with Crosstalk for Transparently Latched Circuits. DATE 2003: 10056-10061 - [c17]Chuan Lin, Hai Zhou:
Retiming for Wire Pipelining in System-On-Chip. ICCAD 2003: 215-220 - [c16]Hai Zhou:
Efficient Steiner tree construction based on spanning graphs. ISPD 2003: 152-157 - 2002
- [j5]Hai Zhou, Narendra V. Shenoy, William Nicholls:
Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81(5): 271-276 (2002) - [c15]Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou:
Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66 - [c14]Hai Zhou:
Clock schedule verification with crosstalk. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 78-83 - 2001
- [j4]Hai Zhou, Adnan Aziz:
Buffer minimization in pass transistor logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 693-697 (2001) - [c13]Hai Zhou, Narendra V. Shenoy, William Nicholls:
Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC 2001: 192-197 - [c12]Hai Zhou, Narendra V. Shenoy, William Nicholls:
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC 2001: 714-719 - 2000
- [j3]Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 819-824 (2000) - [c11]Hai Zhou, D. F. Wong:
Optimal low power X OR gate decomposition. DAC 2000: 104-107 - [c10]Hai Zhou, Adnan Aziz:
Buffer minimization in pass transistor logic. ISPD 2000: 105-110
1990 – 1999
- 1999
- [j2]Hai Zhou, Martin D. F. Wong:
Global routing with crosstalk constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1683-1688 (1999) - [c9]Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99 - [c8]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 - [c7]I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou:
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215 - 1998
- [j1]Hai Zhou, D. F. Wong:
Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998) - [c6]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255 - [c5]Hai Zhou, D. F. Wong:
Global Routing with Crosstalk Constraints. DAC 1998: 374-377 - 1997
- [c4]Hai Zhou, D. F. Wong:
An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580 - [c3]Hai Zhou, D. F. Wong:
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633 - 1996
- [c2]Chung-Ping Chen, Hai Zhou, D. F. Wong:
Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43 - [c1]Hai Zhou, D. F. Wong:
An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315
Coauthor Index
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