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2020 – today
- 2025
[c15]Yuhei Oguro, Yihsin Ho, Jie-Ru Chen, Yi-Jung Chen:
Image Recognition Based Precursor Detection System for Landslide Prevention. SII 2025: 480-485- 2023
- [c14]Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang:
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA 2023: 1140-1152 - 2022
- [c13]Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang:
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC 2022: 122-127 - 2020
- [c12]Chia-Yin Liu
, Yi-Jung Chen, Masanori Hariyama:
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. SAC 2020: 546-553
2010 – 2019
- 2018
- [c11]Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen:
Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories. RACS 2018: 243-248 - 2017
- [j6]Yi-Jung Chen, Wen-Wei Chang, Chia-Yin Liu, Cheng-En Wu, Bo-Yuan Chen, Ming-Ying Tsai:
Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture. IEEE Access 5: 4028-4036 (2017) - [j5]Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang:
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives. IEEE Trans. Computers 66(8): 1457-1463 (2017) - 2015
- [j4]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12(2): 19:19:1-19:19:24 (2015) - [c10]Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu:
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS 2015: 430-436 - 2014
- [c9]Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang:
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs. DATE 2014: 1-6 - 2013
- [c8]Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu:
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED 2013: 304 - 2012
- [c7]Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen:
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. ICCAD 2012: 458-465 - [c6]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD 2012: 67-74 - 2011
- [j3]Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen:
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60(6): 767-782 (2011) - 2010
- [c5]Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang:
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE 2010: 1590-1595
2000 – 2009
- 2009
- [j2]Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang:
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. J. Syst. Archit. 55(5-6): 299-309 (2009) - 2007
- [j1]Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han:
Improved Modulo (2n+1) Multiplier for IDEA. J. Inf. Sci. Eng. 23(3): 911-923 (2007) - [c4]Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen:
Cache leakage control mechanism for hard real-time systems. CASES 2007: 248-256 - [c3]Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su:
An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC 2007: 680-684 - 2006
- [c2]Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen:
Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 523-530 - 2004
- [c1]Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang S. Han:
A New Modulo (2n+1) Multiplier for IDEA. Security and Management 2004: 318-324
Coauthor Index
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