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2000 – 2009
- 2009
[j3]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. IEEE J. Solid State Circuits 44(3): 824-834 (2009)- [c2]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
Insights into wideband fractional All-Digital PLLs for RF applications. CICC 2009: 37-44 - 2006
- [j2]Antonio Liscidini
, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello:
Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. IEEE J. Solid State Circuits 41(12): 2832-2841 (2006) - [c1]Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello:
A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. ISSCC 2006: 1892-1901 - 2005
- [j1]Mario Valla, Giampiero Montagna, Rinaldo Castello, Riccardo Tonietto, Ivan Bietti:
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner. IEEE J. Solid State Circuits 40(4): 970-977 (2005)
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