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2020 – today
- 2022
[c21]Roope Kaivola, Neta Bar Kama:
Timed Causal Fanin Analysis for Symbolic Circuit Simulation. FMCAD 2022: 99-107- [c20]Aarti Gupta, Roope Kaivola, Mihir Parang Mehta, Vaibhav Singh:
Error Correction Code Algorithm and Implementation Verification Using Symbolic Representations. FMCAD 2022: 151-159 - 2021
- [c19]Neta Bar Kama, Roope Kaivola:
Hardware Security Leak Detection by Symbolic Simulation. FMCAD 2021: 34-41
2010 – 2019
- 2015
- [e1]Roope Kaivola, Thomas Wahl:
Formal Methods in Computer-Aided Design, FMCAD 2015, Austin, Texas, USA, September 27-30, 2015. IEEE 2015, ISBN 978-1-5090-4151-0 [contents] - 2013
- [c18]John W. O'Leary, Roope Kaivola, Tom Melham:
Relational STE and theorem proving for formal verification of industrial circuit designs. FMCAD 2013: 97-104 - 2011
- [c17]Roope Kaivola:
Intel CoreTM i7 Processor Execution Engine Validation in a Functional Language Based Formal Framework. PADL 2011: 1
2000 – 2009
- 2009
- [c16]Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik:
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. CAV 2009: 414-429 - 2005
- [j4]T. Karvi, Tienari Tienari, Roope Kaivola:
Stepwise Development of Process-Algebraic Specifications in Decorated Trace Semantics. Formal Methods Syst. Des. 26(3): 293-317 (2005) - [c15]Roope Kaivola:
Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants. CAV 2005: 170-184 - [c14]Roope Kaivola, Armaghan Naik:
Formal verification of high-level conformance with symbolic simulation. HLDVT 2005: 153-159 - 2003
- [j3]Roope Kaivola, Katherine R. Kohatsu:
Proof engineering in the large: formal verification of Pentium?4 floating-point divider. Int. J. Softw. Tools Technol. Transf. 4(3): 323-334 (2003) - 2002
- [c13]Roope Kaivola, Naren Narasimhan:
Formal Verification of the Pentium ® 4 Floating-Point Multiplier. DATE 2002: 20-27 - 2001
- [c12]Roope Kaivola, Katherine R. Kohatsu:
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider. CHARME 2001: 196-211 - [c11]Roope Kaivola, Naren Narasimhan:
Formal verification of the Pentium(R) 4 multiplier. HLDVT 2001: 115-120 - 2000
- [c10]Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger:
Formal verification of iterative algorithms in microprocessors. DAC 2000: 201-206 - [c9]Roope Kaivola, Mark D. Aagaard:
Divider Circuit Verification with Model Checking and Theorem Proving. TPHOLs 2000: 338-355
1990 – 1999
- 1998
- [j2]Roope Kaivola:
Axiomatising Extended Computation Tree Logic. Theor. Comput. Sci. 190(1): 41-60 (1998) - 1997
- [c8]Roope Kaivola:
Using Compositional Preorders in the Verification of Sliding Window Protocal. CAV 1997: 48-59 - 1996
- [c7]Roope Kaivola:
Axiomatising Extended Computation Tree Logic. CAAP 1996: 87-101 - [c6]Roope Kaivola:
Fixpoints for Rabin Tree Automata Make Complementation Easy. ICALP 1996: 312-323 - 1995
- [j1]Roope Kaivola:
On Modal mu-Calculus and Büchi Tree Automata. Inf. Process. Lett. 54(1): 17-22 (1995) - [c5]Roope Kaivola:
Axiomatising Linear Time Mu-calculus. CONCUR 1995: 423-437 - [c4]Roope Kaivola:
A Simple Decision Method for the Linear Time Mu-calculus. STRICT 1995: 190-204 - 1992
- [c3]Roope Kaivola:
Compositional Model Checking for Linear-Time Temporal Logic. CAV 1992: 248-259 - [c2]Roope Kaivola, Antti Valmari:
The Weakest Compositional Semantic Equivalence Preserving Nexttime-less Linear temporal Logic. CONCUR 1992: 207-221 - 1991
- [c1]Roope Kaivola, Antti Valmari:
Using Truth-Preserving Reductions to Improve the Clarity of Kripke-Models. CONCUR 1991: 361-375
Coauthor Index
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