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2020 – today
- 2024
[j16]Leandro Mateus Giacomini Rocha
, Refik Bilgic, Mohamed Naeim, Sudipta Das, Herman Oprins, Amirreza Yousefzadeh, Mario Konijnenburg, Dragomir Milojevic, James Myers, Julien Ryckaert, Dwaipayan Biswas:
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2144-2148 (2024)- [c56]Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim:
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC 2024: 287:1-287:6 - [c55]Michael T. Niemier, Z. Enciso, M. Sharifi, Xiaobo Sharon Hu, Ian O'Connor, A. Graening, R. Sharma, P. Gupta, Jerónimo Castrillón, João Paulo C. de Lima, Asif Ali Khan, H. Farzaneh, N. Afroze, Asif Khan, Julien Ryckaert:
Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers. DATE 2024: 1-10 - [c54]Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS 2024: 1-6 - [c53]Nitish Kumar, Sankatali Venkateswarlu, Yukai Chen, Moritz Brunion, Subrat Mishra, Ankur Gupta, Pushpapraj Singh, Francky Catthoor, James Myers, Julien Ryckaert, Dwaipayan Biswas:
Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. IRPS 2024: 8 - [c52]Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. ISCAS 2024: 1-5 - [c51]Dwaipayan Biswas, James Myers, Srikanth B. Samavedam, Julien Ryckaert:
STCO: Driving the More than Moore Era. ISVLSI 2024: 7-8 - [c50]Yukai Chen, Sankatali Venkateswarlu, Subrat Mishra, Julien Ryckaert, James Myers, Dwaipayan Biswas:
Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet. ISVLSI 2024: 45-50 - [c49]Aakash Patel, Dwaipayan Biswas, Joyjit Kundu, Yoojin Ban, Nicolas Pantano, Arindam Mallik, Julien Ryckaert, James Myers:
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. ISVLSI 2024: 118-123 - [c48]Siva Satyendra Sahoo, Dawit Burusie Abdi, Julien Ryckaert, James Myers, Dwaipayan Biswas:
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. SOCC 2024: 1-6 - [c47]S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits 2024: 1-2 - [c46]Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert:
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j15]Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor:
3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2858-2867 (2023) - [c45]Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor:
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS 2023: 1-5 - [c44]Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert:
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS 2023: 1-7 - [c43]Mohit Kumar Gupta, Manu Perumkunnil, Dwaipayan Biswas, Saeideh Alinezhad Chamazcoti, Gouri Sankar Kar, Arnaud Furnémont, Julien Ryckaert:
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. ISCAS 2023: 1-5 - [c42]Mohit Kumar Gupta, Pieter Weckx, Manu Perumkunnil Komalan, Julien Ryckaert:
Impact of interconnects enhancement on SRAM design beyond 5nm technology node. ISCAS 2023: 1-5 - [c41]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - [c40]S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert:
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j14]Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1497-1506 (2022) - [c39]Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert:
Design enablement of CFET devices for sub-2nm CMOS nodes. DATE 2022: 29-33 - [c38]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c37]Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert:
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits 2022: 365-366 - [c36]Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert:
Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. VLSI Technology and Circuits 2022: 371-372 - [c35]Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - [c34]Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi:
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432 - 2021
- [c33]Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu:
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSCIRC 2021: 55-58 - [c32]Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu:
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSDERC 2021: 55-58 - 2020
- [j13]Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz, Sung Kyu Lim:
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. IEEE Comput. Archit. Lett. 19(1): 51-54 (2020) - [c31]Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert:
Device Scaling roadmap and its implications for Logic and Analog platform. BCICTS 2020: 1-8 - [c30]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC 2020: 34-39 - [c29]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) 2020: 279-300
2010 – 2019
- 2019
- [c28]Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13 - 2017
- [j12]Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq:
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1669-1680 (2017) - [c27]Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta:
SRAM designs for 5nm node and beyond: Opportunities and challenges. ICICDT 2017: 1-4 - 2016
- [c26]Julien Ryckaert:
Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue. ISPD 2016: 89 - 2015
- [c25]Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen:
Holisitic device exploration for 7nm node. CICC 2015: 1-5 - [c24]Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene:
Impact of interconnect multiple-patterning variability on SRAMs. DATE 2015: 609-612 - [c23]Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq:
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT 2015: 1-4 - 2014
- [c22]Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen:
Design Technology co-optimization for N10. CICC 2014: 1-8 - [c21]Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Thomas Knauth, Wojciech M. Barczynski, Gulay Yalcin, Yarco Hayduk, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Julien Ryckaert, Gina Alioto:
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy. DSD 2014: 191-198 - [c20]Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq:
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105 - 2013
- [c19]Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest:
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC 2013: 24:1-24:6 - [c18]Michal Rakowski, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Bradley Snyder, Peter O'Brien, Julien Ryckaert, Philippe Absil, Joris Van Campenhout:
Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter. OFC/NFOEC 2013: 1-3 - 2012
- [j11]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012) - [c17]Jaemin Kim, Sunyoung Kim, Julien Ryckaert, Mikael Detalle, Nele Van Hoovels, Pol Marchal:
A calibrated pathfinding model for signal integrity analysis on interposer. CICC 2012: 1-4 - [c16]Michal Rakowski, Julien Ryckaert, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout:
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator. CICC 2012: 1-6 - 2011
- [c15]Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas:
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. CICC 2011: 1-4 - 2010
- [j10]Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert:
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. IEEE J. Solid State Circuits 45(6): 1198-1208 (2010) - [j9]Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx:
A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler. IEEE J. Solid State Circuits 45(11): 2375-2387 (2010) - [c14]Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx:
An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. DATE 2010: 697-701 - [c13]Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas:
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. ESSCIRC 2010: 418-421
2000 – 2009
- 2009
- [j8]Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(7): 1942-1949 (2009) - [j7]Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas:
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits 44(11): 2873-2880 (2009) - [j6]Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels:
A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS. IEEE J. Solid State Circuits 44(12): 3486-3498 (2009) - [c12]Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas:
A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. ISSCC 2009: 176-177 - [c11]Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels:
A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS. ISSCC 2009: 408-409 - 2008
- [c10]Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx:
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC 2008: 410-413 - [c9]Marian Verhelst, Julien Ryckaert, Yves Vanderperren, Wim Dehaene:
A Low Power, Reconfigurable IR-UWB System. ICC 2008: 3770-3774 - 2007
- [j5]Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas:
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits 42(11): 2515-2527 (2007) - [j4]Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits 42(12): 2860-2869 (2007) - [c8]Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx:
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC 2007: 484-487 - [c7]Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC 2007: 120-591 - [c6]Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke:
Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring 2007: 3135-3139 - 2006
- [j3]Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke:
Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j2]Andrew Fort, Julien Ryckaert, Claude Desset, Philippe De Doncker, Piet Wambacq, Leo Van Biesen:
Ultra-wideband channel model for communication around the human body. IEEE J. Sel. Areas Commun. 24(4): 927-933 (2006) - [c5]Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx:
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC 2006: 368-377 - [c4]Bert Gyselinckx, Ruud J. M. Vullers, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: Emerging Technology for Body Area Networks. VLSI-SoC 2006: 175-180 - [c3]Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: Emerging Technology for Body Area Networks. VLSI-SoC (Selected Papers) 2006: 377-397 - 2005
- [j1]Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx:
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2515-2525 (2005) - [c2]Bert Gyselinckx, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov:
Human++: autonomous wireless sensors for body area networks. CICC 2005: 13-19 - [c1]Andrew Fort, Claude Desset, Julien Ryckaert, Philippe De Doncker, Leo Van Biesen, Stéphane Donnay:
Ultra wide-band body area channel model. ICC 2005: 2840-2844
Coauthor Index
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last updated on 2024-12-02 22:30 CET by the dblp team
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