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2020 – today
- 2024
[j27]Tianchen Gu
, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng:
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 417-430 (2024)- [j26]Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng:
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 667-680 (2024) - [j25]Xuyang Zhao, Tianning Gao, Aidong Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 4178-4189 (2024) - [j24]Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Walter Hu, Dian Zhou:
D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. ACM Trans. Design Autom. Electr. Syst. 29(3): 44:1-44:25 (2024) - [c50]Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC 2024: 671-678 - [c49]Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC 2024: 872-877 - [c48]Tianchen Gu, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng:
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. DAC 2024: 233:1-233:6 - [c47]Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. DAC 2024: 284:1-284:6 - [c46]Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng:
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. DATE 2024: 1-6 - [c45]Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng:
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. DATE 2024: 1-2 - [i5]Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR abs/2409.08534 (2024) - 2023
- [j23]Cuiyang Ding, Yijing Zhou, Wei Cai, Xuan Zeng, Changhao Yan:
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography. J. Comput. Phys. 476: 111862 (2023) - [j22]Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi, Xuan Zeng:
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 347-359 (2023) - [j21]Jiangli Huang, Chuyu Wang, Yuyang Yan, Cong Tao, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng:
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3280-3293 (2023) - [c44]Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng:
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. DAC 2023: 1-6 - 2022
- [j20]Cuiyang Ding, Changhao Yan, Xuan Zeng, Wei Cai:
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions. SIAM J. Sci. Comput. 44(5): 3413- (2022) - [j19]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 1-14 (2022) - [j18]Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng:
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4887-4900 (2022) - [c43]Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou:
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ASP-DAC 2022: 86-91 - [c42]Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng:
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. DAC 2022: 625-630 - [c41]Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng:
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. ICCAD 2022: 50:1-50:9 - [c40]Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng:
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. ISCAS 2022: 2886-2890 - [c39]Hao Jiang, Fan Yang, Changhao Yan, Xuan Zeng:
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing. ISCAS 2022: 3244-3248 - [c38]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. MLCAD 2022: 27-34 - 2021
- [j17]Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 603-607 (2021) - [c37]Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng:
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. ASICON 2021: 1-4 - [c36]Yingqi Li, Fan Yang, Changhao Yan, Xuan Zeng:
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling. ASICON 2021: 1-4 - [c35]Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng:
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. ASICON 2021: 1-4 - [c34]Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. ASP-DAC 2021: 146-151 - [c33]Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng:
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. DAC 2021: 187-192 - [c32]Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng:
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization. DAC 2021: 517-522 - [c31]Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. DATE 2021: 1723-1728 - [c30]Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. ISCAS 2021: 1-5 - [i4]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. CoRR abs/2106.15412 (2021) - [i3]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. CoRR abs/2109.00617 (2021) - 2020
- [c29]Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. DAC 2020: 1-6 - [c28]Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. DATE 2020: 67-72
2010 – 2019
- 2019
- [c27]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu:
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. DAC 2019: 64 - [c26]Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE 2019: 1040-1045 - [c25]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. DATE 2019: 1463-1468 - [i2]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu:
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR abs/1912.00392 (2019) - [i1]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. CoRR abs/1912.00402 (2019) - 2018
- [j16]Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng:
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 531-544 (2018) - [j15]Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng:
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1929-1942 (2018) - [j14]Wenlong Lyu, Pan Xue, Fan Yang, Changhao Yan, Zhiliang Hong, Xuan Zeng, Dian Zhou:
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1954-1967 (2018) - [j13]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng:
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. 23(3): 36:1-36:23 (2018) - [c24]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Multi-objective bayesian optimization for analog/RF circuit synthesis. DAC 2018: 11:1-11:6 - [c23]Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
A general graph based pessimism reduction framework for design optimization of timing closure. DAC 2018: 25:1-25:6 - [c22]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou:
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits. DAC 2018: 132:1-132:6 - [c21]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. ICML 2018: 3312-3320 - 2017
- [j12]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [j11]Mengshuo Wang, Changhao Yan, Xin Li, Dian Zhou, Xuan Zeng:
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 806-819 (2017) - [c20]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c19]Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An efficient algorithm for stencil planning and optimization in E-beam lithography. ASP-DAC 2017: 366-371 - [c18]Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits. DAC 2017: 11:1-11:6 - [c17]Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. DATE 2017: 1195-1200 - [c16]Handi Yu, Changhao Yan, Xuan Zeng, Xin Li:
Impact of circuit-level non-idealities on vision-based autonomous driving systems. ICCAD 2017: 976-983 - [c15]Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Layout decomposition for hybrid E-beam and DSA double patterning lithography. ISCAS 2017: 1-4 - [c14]Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. ISPA/IUCC 2017: 814-821 - 2016
- [j10]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - [c13]Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou:
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. DATE 2016: 1417-1422 - [c12]Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A novel unified dummy fill insertion framework with SQP-based optimization method. ICCAD 2016: 88 - 2015
- [j9]Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng:
Multi-parameter clock skew scheduling. Integr. 48: 129-137 (2015) - [j8]Zhenyu Wu, Changhao Yan, Xuan Zeng, Sheng-Guo Wang:
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method. Integr. 50: 1-15 (2015) - [j7]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - [c11]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC 2015: 652-657 - 2013
- [j6]Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng:
Post-routing layer assignment for double patterning with timing critical paths consideration. Integr. 46(2): 153-164 (2013) - [j5]Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
An efficient method for gradient-aware dummy fill synthesis. Integr. 46(3): 301-309 (2013) - [j4]Changhao Yan, Wei Cai, Xuan Zeng:
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks. SIAM J. Sci. Comput. 35(4) (2013) - [c10]Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD 2013: 170-177 - 2012
- [j3]Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng:
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2172-2181 (2012) - 2011
- [j2]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 402-415 (2011) - [c9]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng:
An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369 - [c8]Changhao Yan, Sheng-Guo Wang, Xuan Zeng:
A new method for multiparameter robust stability distribution analysis of linear analog circuits. ICCAD 2011: 420-427
2000 – 2009
- 2009
- [j1]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1652-1659 (2009) - [c7]Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Provably good and practically efficient algorithms for CMP dummy fill. DAC 2009: 539-544 - 2008
- [c6]Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan:
Efficient techniques for 3-D impedance extraction using mixed boundary element method. ASP-DAC 2008: 158-163 - [c5]Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. DAC 2008: 223-226 - [c4]Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai:
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model. ISQED 2008: 62-67 - [c3]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. ISQED 2008: 718-723 - 2006
- [c2]Changhao Yan, Wenjian Yu, Zeyi Wang:
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method. ASP-DAC 2006: 844-849 - [c1]Changhao Yan, Wenjian Yu, Zeyi Wang:
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. ISQED 2006: 709-716
Coauthor Index
[j27] [j26] [j25] [j24] [c50] [c49] [c48] [c47] [c46] [c45] [i5] [j23] [j22] [j21] [c44] [j20] [j19] [j18] [c43] [c42] [c41] [c40] [c39] [c38] [j17] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [i4] [i3] [c29] [c28] [c27] [c26] [c25] [i2] [i1] [j16] [j15] [j14] [j13] [c24] [c23] [c21] [j12] [j11] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [j10] [c13] [c12] [j9] [j8] [j7] [c11] [j6] [j5] [j4] [c10] [j3] [j2] [c9] [c8] [j1] [c7] [c5] [c4] [c3]
[j27] [j26] [j25] [j24] [c50] [c49] [c48] [c47] [c45] [j22] [j21] [c44] [j19] [j18] [c43] [c42] [c41] [c40] [c38] [c37] [c35] [c34] [c33] [c31] [c30] [i4] [i3] [c29] [c28] [c27] [c26] [c25] [i2] [i1] [j16] [j15] [j14] [j13] [c24] [c23] [c22] [c21] [j12] [j11] [c20] [c19] [c17] [c14] [j10] [c13] [c11]
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