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ORCIDWon-Young Lee
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- Won Young Lee
- Young-Woo Lee (aka: Young Won Lee) — disambiguation page
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2020 – today
- 2024
[j9]Sang-Hun Lee, Won-Young Lee
:
A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4648-4652 (2024)- [c17]Min-Ji Kim, Won-Young Lee:
Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation. ICEIC 2024: 1-3 - [c16]Hyun-Bin Lee, Yoon Heo, Won-Young Lee:
A Wide-Range Reference-Less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition. ISCAS 2024: 1-5 - [c15]Seul-Ki Han, Won-Young Lee:
A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 Signaling. ISOCC 2024: 37-38 - 2023
- [c14]Daewe Kim, Won-Young Lee, Jinwoo Shin, Eung-Hyuk Lee:
A Study on the Assistive System for Safe Elevator Get on of Wheelchair Users with Upper Limb Disability. ICEIC 2023: 1-4 - [c13]Hyun-Bin Lee, Won-Young Lee:
An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery. ISOCC 2023: 111-112 - 2022
- [j8]Dong-Wan Ko, Won-Young Lee:
A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface. IEEE Access 10: 52273-52279 (2022) - [j7]Sang-Hun Lee, Won-Young Lee:
A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction. Sensors 22(16): 6078 (2022) - [c12]Giryong Lee, Won-Young Lee:
A 1.0-V 12-Gb/s Two-FIR Tap DFE with Tap Weighting Adjustable Filters. ICEIC 2022: 1-3 - [c11]Yoon Heo, Won-Young Lee:
A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop Control. ISOCC 2022: 137-138 - 2021
- [c10]Dong-Wan Ko, Won-Young Lee:
A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector. ISCAS 2021: 1-5 - [c9]Sang-Hoon Lee, Won-Young Lee:
A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain Comparison. ISOCC 2021: 7-8 - 2020
- [c8]Eun-Young Jung, Won-Young Lee:
A Fast Locking Duty Cycle Corrector with High Accuracy. ISOCC 2020: 45-46
2010 – 2019
- 2015
- [c7]Chang-Kyo Lee, Min-Su Ahn, Daesik Moon, Kiho Kim, Yoon-Joo Eom, Won-Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon-Young Park, Seung-Jun Bae, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin:
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. VLSIC 2015: 182- - 2013
- [j6]Won-Young Lee, Jiehwan Oh, Lee-Sup Kim:
A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD. IEEE Trans. Circuits Syst. II Express Briefs 60-II(1): 21-25 (2013) - [j5]Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 206-216 (2013) - [c6]Won-Young Lee, Seung-Hyun Lee, Mun-Suck Jang, Eung-Hyuk Lee:
A study on methods for improving the straightness of the intelligent walker to move on slope. URAI 2013: 536-541 - 2012
- [j4]Won-Young Lee, Lee-Sup Kim:
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2518-2528 (2012) - [j3]Won-Young Lee, Kyu-Dong Hwang, Lee-Sup Kim:
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2858-2866 (2012) - [j2]Won-Young Lee, Lee-Sup Kim:
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 964-968 (2012) - 2011
- [j1]Won-Young Lee, Lee-Sup Kim:
A Spread Spectrum Clock Generator for DisplayPort Main Link. IEEE Trans. Circuits Syst. II Express Briefs 58-II(6): 361-365 (2011) - [c5]Won-Young Lee, Lee-Sup Kim:
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. ISCAS 2011: 430-433 - 2010
- [c4]Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim:
A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. ISCAS 2010: 1300-1303 - [c3]Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality. ISSCC 2010: 336-337
2000 – 2009
- 2009
- [c2]Won-Young Lee, Lee-Sup Kim:
A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link. ISCAS 2009: 185-188 - 2007
- [c1]Youngho Park, Won-Young Lee, Kyung Hyune Rhee:
Authenticated On-Demand Ad Hoc Routing Protocol without Pre-shared Key Distribution. BLISS 2007: 41-46
Coauthor Index
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