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2020 – today
- 2023
[j16]Tadayoshi Enomoto, Nobuaki Kobayashi:
Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption. IEICE Trans. Electron. 106(9): 466-476 (2023)
2010 – 2019
- 2019
- [c14]Nobuaki Kobayashi, Tadayoshi Enomoto:
Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply. ASP-DAC 2019: 15-16 - [c13]Nobuaki Kobayashi, Tadayoshi Enomoto:
Low standby power CMOS delay flip-flop with data retention capability. ASP-DAC 2019: 21-22 - 2018
- [j15]Nobuaki Kobayashi, Tadayoshi Enomoto:
Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor. IEICE Trans. Electron. 101-C(8): 671-679 (2018) - [j14]Nobuaki Kobayashi, Tadayoshi Enomoto:
Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply. IEICE Trans. Electron. 101-C(10): 822-830 (2018) - 2015
- [c12]Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto:
A high stability, low supply voltage and low standby power six-transistor CMOS SRAM. ASP-DAC 2015: 10-11 - 2013
- [j13]Tadayoshi Enomoto, Nobuaki Kobayashi:
A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A2BC)". IEICE Trans. Electron. 96-C(4): 424-432 (2013) - [c11]Tadayoshi Enomoto, Nobuaki Kobayashi:
A low power multimedia processor implementing dynamic voltage and frequency scaling technique. ASP-DAC 2013: 75-76 - 2011
- [j12]Tadayoshi Enomoto, Nobuaki Kobayashi:
A Large "Read" and "Write" Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM. IEICE Trans. Electron. 94-C(4): 530-538 (2011)
2000 – 2009
- 2009
- [j11]Tadayoshi Enomoto:
Foreword. IEICE Trans. Electron. 92-C(4): 385 (2009) - [j10]Tadayoshi Enomoto, Nobuaki Kobayashi:
Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit. IEICE Trans. Electron. 92-C(4): 409-416 (2009) - [c10]Tadayoshi Enomoto, Nobuaki Kobayashi, Shimon Isaka:
Fast Sub-sampling Block Matching Algorithm Employing Adaptively Assigned Sizes and Locations of Search Windows. ISCAS 2009: 1653-1656 - 2008
- [j9]Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara:
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. IEICE Trans. Electron. 91-C(4): 553-561 (2008) - [c9]Tadayoshi Enomoto, Yuki Higuchi:
A low-leakage current power 180-nm CMOS SRAM. ASP-DAC 2008: 101-102 - [c8]Nobuaki Kobayashi, Tadayoshi Enomoto:
A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm. ISCAS 2008: 1672-1675 - 2007
- [j8]Tadayoshi Enomoto, Nobuaki Kobayashi, Tomomi Ei:
A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit. IEICE Trans. Electron. 90-C(4): 718-726 (2007) - [c7]Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi:
Low-Power High-Speed 180-nm CMOS Clock Drivers. ASP-DAC 2007: 126-127 - 2006
- [j7]Nobuaki Kobayashi, Tomomi Ei, Tadayoshi Enomoto:
Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits. IEICE Trans. Electron. 89-C(3): 271-279 (2006) - [c6]Tadayoshi Enomoto, Nobuaki Kobayashi:
A low dynamic power and low leakage power 90-nm CMOS square-root circuit. ASP-DAC 2006: 90-91 - 2005
- [c5]Tadayoshi Enomoto, Nobuaki Kobayashi:
A low dynamic power and low leakage power CMOS square-root circuit. ISCAS (2) 2005: 1678-1681 - 2003
- [j6]Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano:
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. IEEE J. Solid State Circuits 38(7): 1220-1226 (2003) - 2001
- [c4]Tadayoshi Enomoto, Akira Kotabe:
A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits. ISCAS (2) 2001: 449-452
1990 – 1999
- 1999
- [c3]Tadayoshi Enomoto, Yasumasa Sasajima, Atsunori Hirobe, Tetsuya Ohsawa:
Fast motion estimation algorithm and low-power CMOS motion estimation array LSI for MPEG-2 encoding. ISCAS (4) 1999: 203-206 - 1994
- [j5]Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura
, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada:
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29(3): 290-297 (1994)
1980 – 1989
- 1989
- [j4]Masakazu Yamashina, Junichi Goto, Fuyuki Okamoto, Koichi Ando, Hachiro Yamada, Tadahiko Horiuchi, Kimiko Nakamura, Tadayoshi Enomoto:
A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. IEEE J. Solid State Circuits 24(6): 1668-1674 (1989) - 1988
- [j3]Hidenobu Harasaki, Ichiro Tamitani, Yukio Endo, Takao Nishitani, Masakatsu Yamashina, Tadayoshi Enomoto, Norio Suzuki:
A single-board video signal processor module employing newly developed LSI devices. IEEE J. Sel. Areas Commun. 6(3): 513-519 (1988) - [j2]Masakazu Yamashina, Tadayoshi Enomoto, Takemitsu Kunio, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Takao Nishitani, Masao Satoh, Koichi Kikuchi:
A microprogrammable real-time video signal processor (VSP) for motion compensation. IEEE J. Solid State Circuits 23(4): 907-915 (1988) - 1987
- [c2]Hidenobu Harasaki, Ichiro Tamitani, Yukio Endo, Takao Nishitani, Masakatsu Yamashina, Tadayoshi Enomoto, Norio Suzuki:
Realtime video signal processor module. ICASSP 1987: 1961-1964 - 1986
- [c1]Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Masakatsu Yamashina, Tadayoshi Enomoto:
Video signal processor configuration by multiprocessor approach. ICASSP 1986: 797-800 - 1984
- [j1]Masa-Aki Yasumoto, Tadayoshi Enomoto, Kohjiro Watanabe, Tsutomu Ishihara:
Single-Chip Adaptive Transversal Filter IC Employing Switched Capacitor Technology. IEEE J. Sel. Areas Commun. 2(2): 324-333 (1984)
Coauthor Index
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