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ORCIDMitchell J. Myjak
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2020 – today
- 2021
[j3]Jun Lu, Huidong Li, Chuan Tian, Mitchell J. Myjak, Jie Xiao, Brian J. Bellgraph, Samuel S. Cartmell, Zhiqun Daniel Deng
:
A Frequency-Programmable Miniaturized Radio Frequency Transmitter for Animal Tracking. Sensors 21(19): 6683 (2021)
2000 – 2009
- 2008
- [j2]Mitchell J. Myjak, José G. Delgado-Frias:
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 14-23 (2008) - 2007
- [j1]Mitchell J. Myjak, José G. Delgado-Frias:
Medium-Grain Cells for Reconfigurable DSP Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(6): 1255-1265 (2007) - 2006
- [c7]Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias:
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. ERSA 2006: 123-129 - [c6]Mitchell J. Myjak, José G. Delgado-Frias:
Superpipelined reconfigurable hardware for DSP. ISCAS 2006 - 2005
- [c5]Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias:
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34 - [c4]Mitchell J. Myjak, José G. Delgado-Frias:
A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164 - 2004
- [c3]Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias:
H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA 2004: 170-176 - [c2]Mitchell J. Myjak, José G. Delgado-Frias:
Pipelined Multipliers for Reconfigurable Hardware. IPDPS 2004 - 2003
- [c1]Mitchell J. Myjak, José G. Delgado-Frias:
A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27
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