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ORCIDKen Choi
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2020 – today
- 2020
[j19]Jongsung Kim, Ken Choi, Damien Sauveron:
Special Issue on Soft Computing for Network and System Security of Internet of Everything. Appl. Soft Comput. 97(Part): 106821 (2020)- [j18]Yunlong Zhang
, Yuan Hong, Ken Choi:
Optimal energy-dissipation control for SOC based balancing in series connected Lithium-ion battery packs. Multim. Tools Appl. 79(23-24): 15923-15944 (2020)
2010 – 2019
- 2019
- [c28]Sayali Patil, Young Bae Kim, Haiqing Nan, Li Li, Ken Choi:
Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB. ISOCC 2019: 237-238 - [c27]Olivier Betschi, Ken Choi:
Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors. ISOCC 2019: 243-244 - [c26]Heekyung Kim, Ken Choi:
The Implementation of a Power Efficient BCNN-Based Object Detection Acceleration on a Xilinx FPGA-SoC. iThings/GreenCom/CPSCom/SmartData 2019: 240-243 - [c25]Heekyung Kim, Ken Choi:
Low Power FPGA-SoC Design Techniques for CNN-based Object Detection Accelerator. UEMCON 2019: 1130-1134 - 2018
- [j17]Seokcheol Lee, SungJin Kim, Ken Choi, Taeshik Shon:
Game theory-based Security Vulnerability Quantification for Social Internet of Things. Future Gener. Comput. Syst. 82: 752-760 (2018) - [c24]Shreyash Patel, YoungBae Kim, Ken Choi:
Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory. ISOCC 2018: 44-45 - [c23]YoungBae Kim, Qiang Tong, Ken Choi, Eunchong Lee, Sung-Joon Jang, Byeong-Ho Choi:
System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles. ISOCC 2018: 151-155 - 2017
- [c22]Yukui Luo, Shuai Li, Kuangyuan Sun, Raul Renteria, Ken Choi:
Implementation of deep learning neural network for real-time object recognition in OpenCL framework. ISOCC 2017: 298-299 - [c21]Kuangyuan Sun, Shuai Li, Yukui Luo, Raul Renteria, Ken Choi:
Highly-efficient parallel convolution acceleration by using multiple GPUs. ISOCC 2017: 300-301 - 2016
- [j16]Eui-Jik Kim, Jung-Hyok Kwon, Ken Choi, Taeshik Shon:
Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices. ACM Trans. Embed. Comput. Syst. 15(2): 40:1-40:17 (2016) - [c20]Heekyung Kim, Ken Choi:
A modular wireless sensor network for architecture of autonomous UAV using dual platform for assisting rescue operation. IEEE SENSORS 2016: 1-3 - [c19]YoungBae Kim, Qiang Tong, Ken Choi, Yunsik Lee:
Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics. ISOCC 2016: 243-244 - [c18]Shuai Li, Ken Choi, Yunsik Lee:
Artificial neural network implementation in FPGA: A case study. ISOCC 2016: 297-298 - [c17]Rahaprian Mudiarasan Premavathi, Qiang Tong, Ken Choi, Yunsik Lee:
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability. ISOCC 2016: 311-312 - 2015
- [j15]Ken Choi, Haiqing Nan, Wook Choi:
Advances in Smart and Intelligent Multimedia Platforms for Pervasive Computing. Multim. Tools Appl. 74(5): 1537-1539 (2015) - 2014
- [j14]Jongsung Kim, Ken Choi, Wook Choi:
Advanced Convergence Technologies and Practices for Wireless Ad Hoc and Sensor Networks. Int. J. Distributed Sens. Networks 10 (2014) - [j13]Yunlong Zhang, Joohee Kim, Ken Choi, Taeshik Shon:
High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions. Int. J. Distributed Sens. Networks 10 (2014) - 2013
- [j12]Jaeik Cho, Setiawan Soekamtoputra, Ken Choi, Jongsub Moon:
Power dissipation and area comparison of 512-bit and 1024-bit key AES. Comput. Math. Appl. 65(9): 1378-1383 (2013) - [j11]Jaeik Cho, Taeshik Shon, Ken Choi, Jongsub Moon:
Dynamic learning model update of hybrid-classifiers for intrusion detection. J. Supercomput. 64(2): 522-526 (2013) - [j10]Li Li, Ken Choi, Haiqing Nan:
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1540-1544 (2013) - 2012
- [j9]Haiqing Nan, Ken Choi:
Low cost and highly reliable hardened latch design for nanoscale CMOS technology. Microelectron. Reliab. 52(6): 1209-1214 (2012) - [j8]Yu-Chi Tsao, Ken Choi:
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 371-375 (2012) - [j7]Haiqing Nan, Ken Choi:
High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1445-1457 (2012) - [j6]Yu-Chi Tsao, Ken Choi:
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 366-371 (2012) - [c16]Yu-Chi Tsao, Ken Choi:
Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length. ISCAS 2012: 998-1001 - [c15]Haiqing Nan, Ken Choi:
Soft error tolerant latch design with low cost for nanoelectronic systems. ISCAS 2012: 1572-1575 - [c14]Yunlong Zhang, Qiang Tong, Li Li, Wei Wang, Ken Choi, JongEun Jang, Hyobin Jung, Si-Young Ahn:
Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes. ISOCC 2012: 21-24 - [c13]Haiqing Nan, Wei Wang, Ken Choi:
Circuit design for carbon nanotube field effect transistors. ISOCC 2012: 351-354 - [c12]Haiqing Nan, Li Li, Ken Choi:
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology. ISQED 2012: 328-333 - 2011
- [j5]Li Li, Ken Choi:
Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications. IET Commun. 5(17): 2501-2508 (2011) - [j4]Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi:
Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits. J. Inf. Process. Syst. 7(1): 93-102 (2011) - [j3]Haiqing Nan, Ken Choi:
Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology. Microelectron. Reliab. 51(12): 2086-2092 (2011) - [c11]Yu-Chi Tsao, Ken Choi:
Hardware-efficient parallel FIR digital filter structures for symmetric convolutions. ISCAS 2011: 2301-2304 - [c10]Peiwen He, Wei Wang, Ken Choi, Jonghyun Lee, Soohyun Kim:
Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting. ISOCC 2011: 450-453 - [c9]Li Li, Ken Choi, Haiqing Nan:
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. ISQED 2011: 74-79 - [c8]Sandeep Sriram, Haiqing Nan, Ken Choi:
Low power latch design in near sub-threshold region to improve reliability for soft error. ISQED 2011: 611-614 - 2010
- [j2]Kyung Ki Kim, Wei Wang, Ken Choi:
On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 798-802 (2010) - [c7]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Power gating for ultra-low voltage nanometer ICs. ISCAS 2010: 1472-1475 - [c6]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Adaptive HCI-aware power gating structure. ISQED 2010: 219-224 - [c5]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Hybrid MOSFET/CNFET based power gating structure. SoCC 2010: 334-338
2000 – 2009
- 2009
- [j1]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage. IEEE Trans. Circuits Syst. II Express Briefs 56-II(12): 926-930 (2009) - [c4]Li Li, Ken Choi, Seongmo Park, MooKyung Chung:
Selective clock gating by using wasting toggle rate. EIT 2009: 399-404 - [c3]Feng Ge, Pranjal Jain, Ken Choi:
Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology. EIT 2009: 405-410 - [c2]Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin:
Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126 - 2008
- [c1]Jerry Frenkil, Ken Choi, Kimiyoshi Usami:
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE 2008
Coauthor Index
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