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2010 – 2019
- 2016
[j4]Miroslaw Chmiel
, Józef Kulisz, Robert Czerwinski, A. Krzyzyk, Marcin Rosol, Patryk Smolarek:
An IEC 61131-3-based PLC implemented by means of an FPGA. Microprocess. Microsystems 44: 28-37 (2016)- [j3]Robert Czerwinski, Dariusz Kania:
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. ACM Trans. Design Autom. Electr. Syst. 22(1): 3:1-3:25 (2016) - 2015
- [c8]Tomasz Rudnicki, Robert Czerwinski, Dariusz Polok, Andrzej Sikora:
Performance analysis of a PMSM drive with torque and speed control. MIXDES 2015: 562-566 - 2013
- [c7]Robert Czerwinski, Miroslaw Chmiel, Wojciech Wygrabek:
FPGA Implementation of Programmable Logic Controller Compliant with EN 61131-3. PDeS 2013: 138-143 - 2012
- [j2]Robert Czerwinski, Dariusz Kania:
Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocess. Microsystems 36(1): 45-61 (2012) - 2010
- [c6]Józef Kulisz, Robert Czerwinski, Jan Mocha, Miroslaw Chmiel:
A PC-based object simulator for supporting PLC software development. PDeS 2010: 215-220 - [c5]Piotr Foltyn, Przemyslaw Flak, Robert Czerwinski, Tomasz Rudnicki:
The virtual drum kit. PDeS 2010: 232-235
2000 – 2009
- 2009
- [j1]Robert Czerwinski, Dariusz Kania:
Synthesis of finite state machines for CPLDs. Int. J. Appl. Math. Comput. Sci. 19(4): 647-659 (2009) - [c4]Robert Czerwinski, Dariusz Kania:
CPLD-oriented Synthesis of Finite State Machines. DSD 2009: 521-528 - [c3]Robert Czerwinski, Józef Kulisz:
State machine description oriented towards effective usage of vendor-independent synthesis tools. PDeS 2009: 27-32 - [c2]Robert Czerwinski, Dariusz Kania:
State assignment and logic optimization for finite state machines. PDeS 2009: 39-44 - 2005
- [c1]Robert Czerwinski, Dariusz Kania:
State Assignment for PAL-based CPLDs. DSD 2005: 127-134
Coauthor Index
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