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ORCIDHuawei Li 0001
Person information
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
- affiliation (PhD 2001): Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China
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2020 – today
- 2025
[j93]Zhiteng Chao
, Xindi Zhang, Junying Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li:
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. Integr. 100: 102265 (2025)- 2024
- [j92]Xiaoze Lin, Liyang Lai, Huawei Li:
Parallel Static Learning Toward Heterogeneous Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 983-993 (2024) - [j91]Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li:
PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1246-1259 (2024) - [j90]Lian Liu, Ying Wang, Xiandong Zhao, Weiwei Chen, Huawei Li, Xiaowei Li, Yinhe Han:
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1497-1510 (2024) - [j89]Mingkai Chen, Cheng Liu, Shengwen Liang, Lei He, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li:
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1781-1793 (2024) - [j88]Yintao He, Bing Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2635-2646 (2024) - [j87]Ying Zhang, Aodi He, Jiaying Li, Ahmed Rezine, Zebo Peng, Erik Larsson, Tao Yang, Jianhui Jiang, Huawei Li:
On Modeling and Detecting Trojans in Instruction Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3226-3239 (2024) - [j86]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. 19: 6604-6619 (2024) - [j85]Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li:
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1325-1335 (2024) - [c188]Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li:
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. ASPDAC 2024: 58-64 - [c187]Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao:
iEDA: An Open-source infrastructure of EDA. ASPDAC 2024: 77-82 - [c186]Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li:
APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. ASPDAC 2024: 231-237 - [c185]Zhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li:
A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. ASPDAC 2024: 503-508 - [c184]Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li:
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. DAC 2024: 26:1-26:6 - [c183]Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC 2024: 60:1-60:6 - [c182]Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han:
Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. DAC 2024: 140:1-140:6 - [c181]Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han:
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. DAC 2024: 243:1-243:6 - [c180]Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Huawei Li:
SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. DAC 2024: 296:1-296:6 - [c179]Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han:
GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. DATE 2024: 1-6 - [c178]Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang:
Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. DATE 2024: 1-6 - [c177]Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li, Xiaowei Li:
HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. DATE 2024: 1-6 - [c176]Han Yan, Shuai Chen, Junying Huang, Jing Ye, Huawei Li, Xiaowei Li:
A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. ETS 2024: 1-4 - [c175]Yunkun Liao, Hanyue Lin, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan:
Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. Euro-Par (2) 2024: 259-273 - [c174]Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li:
A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. ITC-Asia 2024: 1-6 - [c173]Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li:
Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. ITC-Asia 2024: 1-6 - [i28]Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR abs/2403.11202 (2024) - [i27]Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang:
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. CoRR abs/2407.08473 (2024) - [i26]Qing Zhang, Cheng Liu, Siting Liu, Yajuan Hui, Huawei Li, Xiaowei Li:
ApproxPilot: A GNN-based Accelerator Approximation Framework. CoRR abs/2407.11324 (2024) - [i25]Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li:
SigDLA: A Deep Learning Accelerator Extension for Signal Processing. CoRR abs/2407.12565 (2024) - [i24]Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Cheng Liu, Huawei Li, Xiaowei Li:
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. CoRR abs/2407.12575 (2024) - [i23]Zesong Jiang, Qing Zhang, Cheng Liu, Huawei Li, Xiaowei Li:
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. CoRR abs/2407.12576 (2024) - 2023
- [j84]Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
Chosen ciphertext correlation power analysis on Kyber. Integr. 91: 10-22 (2023) - [j83]Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li:
On-Line Fault Protection for ReRAM-Based Neural Networks. IEEE Trans. Computers 72(2): 423-437 (2023) - [j82]Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li:
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1504-1517 (2023) - [j81]Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li:
Statistical Modeling of Soft Error Influence on Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4152-4163 (2023) - [j80]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. J. Supercomput. 79(3): 2819-2849 (2023) - [j79]Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li:
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. ACM Trans. Design Autom. Electr. Syst. 28(4): 67:1-67:23 (2023) - [j78]Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1763-1773 (2023) - [j77]Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Soft Error Reliability Analysis of Vision Transformers. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2126-2136 (2023) - [c172]Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li:
A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. ATS 2023: 1-6 - [c171]Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Pengyu Tian, Huawei Li:
Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning. ATS 2023: 1-6 - [c170]Wen Li, Ying Wang, Kaiwei Zou, Huawei Li, Xiaowei Li:
Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. ATS 2023: 1-6 - [c169]Huawei Li, Jing Ye, Wei Hu, Jiliang Zhang:
Message from the Chairs. ATS 2023: 1 - [c168]Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li:
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. ATS 2023: 1-6 - [c167]Yipei Yang, Junying Huang, Zongyue Wang, Jing Ye, Zihao Sun, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
A Template Attack on Reduction Without Reference Device on Kyber. ATS 2023: 1-6 - [c166]Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han:
APPEND: Rethinking ASIP Synthesis in the Era of AI. DAC 2023: 1-6 - [c165]Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li:
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE 2023: 1-2 - [c164]Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo:
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. DATE 2023: 1-6 - [c163]Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li:
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. ETS 2023: 1-6 - [c162]Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. ICCAD 2023: 1-9 - [c161]Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng:
Fast Exact NPN Classification with Influence-Aided Canonical Form. ICCAD 2023: 1-9 - [c160]Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han:
PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. ICCD 2023: 263-266 - [c159]Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li:
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. ICCD 2023: 336-343 - [c158]Kaiwei Zou, Songyun Qu, Wen Li, Ying Wang, Huawei Li, Yongpan Liu:
Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. ICPADS 2023: 1123-1130 - [i22]Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo:
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. CoRR abs/2301.12122 (2023) - [i21]Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Reliability Analysis of Vision Transformers. CoRR abs/2302.10468 (2023) - [i20]Xinghua Xue, Cheng Liu, Haitong Huang, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. CoRR abs/2302.10469 (2023) - [i19]Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
ChipGPT: How far are we from natural language hardware design. CoRR abs/2305.14019 (2023) - [i18]Haitong Huang, Cheng Liu, Xinghua Xue, Ying Wang, Huawei Li, Xiaowei Li:
MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. CoRR abs/2306.11758 (2023) - [i17]Xingquan Li, Simin Tao, Zengrong Huang, Shijian Chen, Zhisheng Zeng, Liwei Ni, Zhipeng Huang, Chunan Zhuang, Hongxi Wu, Weiguo Li, Xueyan Zhao, He Liu, Shuaiying Long, Wei He, Bojun Liu, Sifeng Gan, Zihao Yu, Tong Liu, Yuchi Miao, Zhiyuan Yan, Hao Wang, Jie Zhao, Yifan Li, Ruizhi Liu, Xiaoze Lin, Bo Yang, Zhen Xue, Fuxing Huang, Zonglin Yang, Zhenggang Wu, Jiangkao Li, Yuezuo Liu, Ming Peng, Yihang Qiu, Wenrui Wu, Zheqing Shao, Kai Mo, Jikang Liu, Yuyao Liang, Mingzhe Zhang, Zhuang Ma, Xiang Cong, Daxiang Huang, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Biwei Xie, Yungang Bao:
iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library. CoRR abs/2308.01857 (2023) - [i16]Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance. CoRR abs/2308.08230 (2023) - [i15]Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. CoRR abs/2308.11334 (2023) - [i14]Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng:
Fast Exact NPN Classification with Influence-aided Canonical Form. CoRR abs/2308.12311 (2023) - [i13]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR abs/2309.10607 (2023) - [i12]Qing Zhang, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Huawei Li, Xiaowei Li:
Cross-Layer Optimization for Fault-Tolerant Deep Learning. CoRR abs/2312.13754 (2023) - [i11]Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li:
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. CoRR abs/2312.14536 (2023) - [i10]Liwei Ni, Zonglin Yang, Jiaxi Zhang, Changhong Feng, Jianhua Liu, Guojie Luo, Huawei Li, Biwei Xie, Xingquan Li:
MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. CoRR abs/2312.14541 (2023) - 2022
- [j76]Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li:
Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. CCF Trans. High Perform. Comput. 4(3): 302-320 (2022) - [j75]Kaiwei Zou, Ying Wang, Long Cheng, Songyun Qu, Huawei Li, Xiaowei Li:
CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. IEEE Trans. Computers 71(7): 1626-1639 (2022) - [j74]Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li:
A Fast Precision Tuning Solution for Always-On DNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1236-1248 (2022) - [j73]Yintao He, Ying Wang, Huawei Li, Xiaowei Li:
Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2115-2127 (2022) - [j72]Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li:
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2808-2820 (2022) - [j71]Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3400-3413 (2022) - [j70]Aijiao Cui, Zhen Weng, Hui Zhang, Gang Qu, Huawei Li:
SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. IEEE Trans. Emerg. Top. Comput. 10(4): 2025-2041 (2022) - [j69]Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 418-431 (2022) - [j68]Ying Zhang, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang:
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1677-1690 (2022) - [c157]Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. ASP-DAC 2022: 672-677 - [c156]Hao Huang, Haihua Shen, Shan Li, Huawei Li:
A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features. ATS 2022: 138-143 - [c155]Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li:
InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. DAC 2022: 97-102 - [c154]Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li:
VStore: in-storage graph based vector search accelerator. DAC 2022: 997-1002 - [c153]Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. DATE 2022: 1035-1040 - [c152]Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li:
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD 2022: 42:1-42:9 - [c151]Lei Dai, Ying Wang, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li:
Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. ICCD 2022: 42-49 - [c150]Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao:
Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. ISOCC 2022: 211-212 - [c149]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
SASH: Efficient secure aggregation based on SHPRG for federated learning. UAI 2022: 1243-1252 - [c148]Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li:
Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. VTS 2022: 1-12 - [i9]Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li:
Fault-Tolerant Deep Learning: A Hierarchical Perspective. CoRR abs/2204.01942 (2022) - [i8]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning. CoRR abs/2208.07189 (2022) - [i7]Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li:
Statistical Modeling of Soft Error Influence on Neural Networks. CoRR abs/2210.05876 (2022) - 2021
- [j67]Jifeng He, Chenggang Wu, Huawei Li, Yang Guo, Tao Li:
Editorial for the special issue on reliability and power efficiency for HPC. CCF Trans. High Perform. Comput. 3(1): 1-3 (2021) - [j66]Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. CCF Trans. High Perform. Comput. 3(1): 85-100 (2021) - [j65]Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li:
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE Trans. Computers 70(9): 1511-1525 (2021) - [j64]Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li:
An Edge 3D CNN Accelerator for Low-Power Activity Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 918-930 (2021) - [j63]Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Shuang Zhao, Lei Zhang, Huaguo Liang, Huawei Li, Kwang-Ting Cheng:
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 472-484 (2021) - [j62]Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1955-1966 (2021) - [c147]Yunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li:
SeGa: A Trojan Detection Method Combined With Gate Semantics. ATS 2021: 43-48 - [c146]Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li:
GCiM: A Near-Data Processing Accelerator for Graph Construction. DAC 2021: 205-210 - [c145]Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. DAC 2021: 577-582 - [c144]Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li:
PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. DAC 2021: 811-816 - [c143]Xiaoze Lin, Liyang Lai, Huawei Li:
Scalable Parallel Static Learning. ITC-Asia 2021: 1-6 - [c142]Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li:
GLIST: Towards In-Storage Graph Learning. USENIX ATC 2021: 225-238 - [c141]Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo:
Special Session - Test for AI Chips: from DFT to On-line Testing. VTS 2021: 1 - [i6]Dawen Xu, Qianlong Wang, Cheng Liu, Cheng Chu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning. CoRR abs/2106.04772 (2021) - [i5]Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
Energy-Efficient Accelerator Design for Deformable Convolution Networks. CoRR abs/2107.02547 (2021) - [i4]Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors. CoRR abs/2107.03096 (2021) - [i3]Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR abs/2108.05023 (2021) - [i2]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
Efficient Secure Aggregation Based on SHPRG For Federated Learning. CoRR abs/2111.12321 (2021) - 2020
- [j61]Qingli Guo, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li:
MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access 8: 63368-63380 (2020) - [j60]Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li:
Evaluating and Constraining Hardware Assertions with Absent Scenarios. J. Comput. Sci. Technol. 35(5): 1198-1216 (2020) - [j59]Liyang Lai, Kun-Han Tsai, Huawei Li:
GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 239-247 (2020) - [j58]Ying Zhang, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li, Petru Eles, Jianhui Jiang:
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 714-727 (2020) - [j57]Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li:
Architecting Effectual Computation for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2654-2667 (2020) - [j56]Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li:
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4524-4536 (2020) - [c140]Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng:
Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. ASAP 2020: 85-92 - [c139]Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu:
Survey: Hardware Trojan Detection for Netlist. ATS 2020: 1-6 - [c138]Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li:
Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. ATS 2020: 1-6 - [c137]Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li:
Towards State-Aware Computation in ReRAM Neural Networks. DAC 2020: 1-6 - [c136]Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
An Efficient Deep Learning Accelerator for Compressed Video Analysis. DAC 2020: 1-6 - [c135]Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li:
CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. DATE 2020: 963-966 - [c134]Jiaqi Zhang, Ying Zhang, Huawei Li, Jianhui Jiang:
HIT: A Hidden Instruction Trojan Model for Processors. DATE 2020: 1271-1274 - [c133]Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang, Huawei Li:
Multi-task Scheduling for PIM-based Heterogeneous Computing System. ACM Great Lakes Symposium on VLSI 2020: 457-462 - [c132]Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li:
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI 2020: 537-542 - [c131]Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li:
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. ICCAD 2020: 46:1-46:7 - [c130]Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. ICCAD 2020: 72:1-72:9 - [c129]Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui:
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. VTS 2020: 1-10 - [c128]Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu:
Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS 2020: 1-6 - [c127]Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li:
A New Secure Scan Design with PUF-based Key for Authentication. VTS 2020: 1-6
2010 – 2019
- 2019
- [j55]Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu:
Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access 7: 85055-85065 (2019) - [j54]Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. ACM J. Emerg. Technol. Comput. Syst. 15(4): 35:1-35:25 (2019) - [j53]Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li:
Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 767-779 (2019) - [j52]Ying Wang, Huawei Li, Long Cheng, Xiaowei Li:
A QoS-QoR Aware CNN Accelerator Design Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 1995-2007 (2019) - [j51]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c126]Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Yulin Dai, Long Cheng, Huawei Li, Lei Zhang:
Resilient Neural Network Training for Accelerators with Computing Errors. ASAP 2019: 99-102 - [c125]Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li:
Exploring emerging CNFET for efficient last level cache design. ASP-DAC 2019: 426-431 - [c124]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
P3M: a PIM-based neural network model protection scheme for deep learning accelerator. ASP-DAC 2019: 633-638 - [c123]Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li:
GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. ATS 2019: 111-116 - [c122]Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li:
A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. DAC 2019: 202 - [c121]Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li:
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. DAC 2019: 210 - [c120]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. DATE 2019: 1172-1177 - [c119]Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. FPL 2019: 173-179 - [c118]Yintao He, Ying Wang, Yongchen Wang, Huawei Li, Xiaowei Li:
An Agile Precision-Tunable CNN Accelerator based on ReRAM. ICCAD 2019: 1-7 - [c117]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. ICCD 2019: 91-99 - [c116]Jing Chen, Hui Zheng, Peng Li, Zhenjiang Zhang, Huawei Li, Wei Liu:
Fuzzy Association Rule Mining Algorithm Based on Load Classifier. ICDS 2019: 178-191 - [c115]Kuozhong Zhang, Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS 2019: 287-292 - [c114]Huawei Li, Xiaowei Li, Yinhe Han:
China Test Conference (CTC) - Extending the Global Test Forum to China. ITC 2019: 1-4 - [c113]Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu:
Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia 2019: 37-42 - [c112]Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia 2019: 49-54 - [c111]Li Li, Dawen Xu, Kouzi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
Squeezing the Last MHz for CNN Acceleration on FPGAs. ITC-Asia 2019: 151-156 - [c110]Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li:
A Memristor-based Scan Hold Flip-Flop. NVMSA 2019: 1-2 - [c109]Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li:
Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. USENIX ATC 2019: 395-410 - [c108]Aijiao Cui, Yan Yang, Gang Qu, Huawei Li:
A Secure and Low-overhead Active IC Metering Scheme. VTS 2019: 1-6 - [c107]Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. VTS 2019: 1-6 - [i1]Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li:
HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR abs/1906.06996 (2019) - 2018
- [j50]Faqiang Sun, Guihai Yan, Xin He, Huawei Li, Yinhe Han:
CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. J. Comput. Sci. Technol. 33(1): 131-144 (2018) - [j49]Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1265-1277 (2018) - [j48]Ying Wang, Huawei Li, Xiaowei Li:
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1971-1984 (2018) - [j47]Yun Cheng, Huawei Li, Ying Wang, Haihua Shen, Bo Liu, Xiaowei Li:
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2166-2179 (2018) - [j46]Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li:
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 720-732 (2018) - [c106]Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu:
Bias PUF based Secure Scan Chain Design. AsianHOST 2018: 31-36 - [c105]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
XORiM: A case of in-memory bit-comparator implementation and its performance implications. ASP-DAC 2018: 349-354 - [c104]Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li:
A low-overhead PUF based on parallel scan design. ASP-DAC 2018: 715-720 - [c103]Wei Zhao, Haihua Shen, Huawei Li, Xiaowei Li:
Hardware Trojan Detection Based on Signal Correlation. ATS 2018: 80-85 - [c102]Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li:
A New Scheme to Extract PUF Information by Scan Chain. ATS 2018: 104-108 - [c101]Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li:
A retrospective evaluation of energy-efficient object detection solutions on embedded devices. DATE 2018: 709-714 - [c100]Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li:
FCN-engine: accelerating deconvolutional layers in classic CNN processors. ICCAD 2018: 22 - [c99]Ying Wang, Wen Li, Huawei Li, Xiaowei Li:
Lightweight Timing Channel Protection for Shared DRAM Controller. ITC 2018: 1-10 - [c98]Ying Wang, Wen Li, Huawei Li, Xiaowei Li:
Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. ITC-Asia 2018: 73-78 - [c97]Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang:
Small Trojan Testing Using Bounded Model Checking. ITC-Asia 2018: 85-90 - [c96]Sohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li:
Innovative practices on challenges, opportunities, and solutions to hardware security. VTS 2018: 1 - [c95]Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li:
Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS 2018: 1-6 - 2017
- [j45]Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu:
Why current secure scan designs fail and how to fix them? Integr. 56: 105-114 (2017) - [j44]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 705-718 (2017) - [j43]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j42]Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li:
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1285-1296 (2017) - [j41]Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, Xiaowei Li:
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2736-2748 (2017) - [c94]Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. ASP-DAC 2017: 396-401 - [c93]Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li:
A New Active IC Metering Technique Based on Locking Scan Cells. ATS 2017: 40-45 - [c92]Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu:
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? ATS 2017: 121-126 - [c91]Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon:
Test and Reliability of Emerging Non-volatile Memories. ATS 2017: 175-183 - [c90]Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li:
On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. ATS 2017: 195-200 - [c89]Dawen Xu, Yi Liao, Ying Wang, Huawei Li, Xiaowei Li:
Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. Conf. Computing Frontiers 2017: 255-258 - [c88]Ying Wang, Huawei Li, Xiaowei Li:
Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. DAC 2017: 33:1-33:6 - [c87]Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang:
Software-based online self-testing of network-on-chip using bounded model checking. ITC 2017: 1-10 - [c86]Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li:
Flip-flop clustering based trace signal selection for post-silicon debug. VTS 2017: 1-6 - [c85]Huawei Li, Xiaowei Li:
Innovative practices session 10C formal verification practices in industry. VTS 2017: 1 - 2016
- [j40]Jun Zhou, Huawei Li, Tiancheng Wang, Xiaowei Li:
LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. Integr. 52: 41-50 (2016) - [j39]Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li:
CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. IEEE Trans. Computers 65(3): 716-729 (2016) - [j38]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu:
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 285-297 (2016) - [j37]Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li:
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 999-1011 (2016) - [j36]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. 21(2): 27:1-27:14 (2016) - [j35]Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li:
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 858-870 (2016) - [j34]Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li:
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1613-1625 (2016) - [c84]Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li:
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. ATS 2016: 43-48 - [c83]Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li:
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC 2016: 37:1-37:6 - [c82]Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li:
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC 2016: 110:1-110:6 - [c81]Ying Wang, Huawei Li, Xiaowei Li:
Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. DATE 2016: 1164-1167 - [c80]Faqiang Sun, Huawei Li, Yinhe Han, Guihai Yan, Jun Ma:
PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. IGSC 2016: 1-8 - [c79]Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li:
An ultra-low overhead LUT-based PUF for FPGA. AsianHOST 2016: 1-6 - [c78]Ying Wang, Huawei Li, Xiaowei Li:
Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. ICCAD 2016: 13 - [c77]Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li:
A new countermeasure against scan-based side-channel attacks. ISCAS 2016: 1722-1725 - [c76]Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu:
An accurate algorithm for computing mutation coverage in model checking. ITC 2016: 1-10 - [c75]Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li:
Path constraint solving based test generation for observability-enhanced branch coverage. VTS 2016: 1-6 - 2015
- [j33]Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li:
An on-chip frequency programmable test clock generation and application method for small delay defect detection. Integr. 49: 87-97 (2015) - [j32]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li:
Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 493-506 (2015) - [j31]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 879-892 (2015) - [c74]Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin:
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. ASP-DAC 2015: 514-519 - [c73]Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li:
A Lightweight Timing Channel Protection for Shared Memory Controllers. ATS 2015: 55-60 - [c72]Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li:
TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. ATS 2015: 85-90 - [c71]Jun Zhou, Huawei Li, Tiancheng Wang, Ying Wang, Xiaowei Li:
TURO: A lightweight turn-guided routing scheme for 3D NoCs. COOL Chips 2015: 1-3 - [c70]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. DAC 2015: 19:1-19:6 - [c69]Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li:
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC 2015: 47:1-47:6 - [c68]Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita:
Temperature-aware software-based self-testing for delay faults. DATE 2015: 423-428 - [c67]Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. DATE 2015: 593-596 - [c66]Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li:
A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537 - [c65]Yun Cheng, Ying Wang, Huawei Li, Xiaowei Li:
A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. ISVLSI 2015: 368-373 - [c64]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT 2015: 1-4 - 2014
- [j30]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li:
Reinventing Memory System Design for Many-Accelerator Architecture. J. Comput. Sci. Technol. 29(2): 273-280 (2014) - [j29]Shuangde Fang, Zidong Du, Yuntan Fang, Yuanjie Huang, Yang Chen, Lieven Eeckhout, Olivier Temam, Huawei Li, Yunji Chen, Chengyong Wu:
Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach. ACM Trans. Archit. Code Optim. 11(2): 21:1-21:25 (2014) - [j28]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 113-126 (2014) - [j27]Yuntan Fang, Huawei Li, Xiaowei Li:
Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1450-1455 (2014) - [j26]Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li:
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1738-1749 (2014) - [c63]Yun Cheng, Huawei Li, Xiaowei Li:
An On-Line Timing Error Detection Method for Silicon Debug. ATS 2014: 263-268 - [c62]Ying Wang, Yinhe Han, Huawei Li:
A low power DRAM refresh control scheme for 3D memory cube. COOL Chips 2014: 1-3 - [c61]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li:
Functional test generation guided by steady-state probabilities of abstract design. DATE 2014: 1-4 - [c60]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li:
Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. ICCAD 2014: 295-300 - [c59]Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li:
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. ISVLSI 2014: 392-397 - [c58]Jian Wang, Huawei Li, Xiaowei Li:
A novel abstraction-guided simulation approach using posterior probabilities for verification. VLSI-DAT 2014: 1-4 - 2013
- [j25]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 821-833 (2013) - [j24]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1210-1219 (2013) - [j23]Ying Zhang, Huawei Li, Xiaowei Li:
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1220-1233 (2013) - [c57]Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li:
Path Constraint Solving Based Test Generation for Hard-to-Reach States. Asian Test Symposium 2013: 239-244 - [c56]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li:
Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. ISCAS 2013: 337-340 - [c55]Yuntan Fang, Huawei Li, Xiaowei Li:
RSAK: Random stream attack for phase change memory in video applications. VTS 2013: 1-6 - 2012
- [j22]Xiang Fu, Huawei Li, Xiaowei Li:
Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 236-247 (2012) - [j21]Songwei Pei, Huawei Li, Xiaowei Li:
A High-Precision On-Chip Path Delay Measurement Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1565-1577 (2012) - [j20]Songwei Pei, Huawei Li, Xiaowei Li:
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2157-2169 (2012) - [c54]Yuntan Fang, Huawei Li, Xiaowei Li:
SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. Asian Test Symposium 2012: 131-136 - [c53]Xuefeng Zhu, Huawei Li, Xiaowei Li:
Statistical SDFC: A metric for evaluating test quality of small delay faults. VLSI-DAT 2012: 1-4 - 2011
- [j19]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Trans. Inf. Syst. 94-D(4): 809-821 (2011) - [j18]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integr. 44(3): 185-191 (2011) - [j17]Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li:
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1787-1800 (2011) - [j16]Minjin Zhang, Huawei Li, Xiaowei Li:
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1969-1982 (2011) - [c52]Yuntan Fang, Huawei Li, Xiaowei Li:
A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. Asian Test Symposium 2011: 329-334 - [c51]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE 2011: 968-973 - [c50]Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li:
An abacus turn model for time/space-efficient reconfigurable routing. ISCA 2011: 259-270 - [c49]Songwei Pei, Huawei Li, Xiaowei Li:
A unified test architecture for on-line and off-line delay fault detections. VTS 2011: 272-277 - 2010
- [j15]Xiang Fu, Huawei Li, Xiaowei Li:
Testable Critical Path Selection Considering Process Variation. IEICE Trans. Inf. Syst. 93-D(1): 59-67 (2010) - [c48]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Graph partition based path selection for testing of small delay defects. ASP-DAC 2010: 499-504 - [c47]Xiang Fu, Huawei Li, Xiaowei Li:
On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. Asian Test Symposium 2010: 45-48 - [c46]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium 2010: 117-120 - [c45]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium 2010: 319-324 - [c44]Ying Zhang, Huawei Li, Xiaowei Li:
Software-Based Self-Testing of Processors Using Expanded Instructions. Asian Test Symposium 2010: 415-420 - [c43]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE 2010: 933-936 - [c42]Songwei Pei, Huawei Li, Xiaowei Li:
An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE 2010: 1353-1356 - [c41]Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li:
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC 2010: 343-352 - [c40]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
On generation of a universal path candidate set containing testable long paths. ITC 2010: 816 - [c39]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC 2010: 70-76 - [c38]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Fast path selection for testing of small delay defects considering path correlations. VTS 2010: 3-8
2000 – 2009
- 2009
- [j14]Ying Zhang, Huawei Li, Xiaowei Li:
Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. J. Comput. Sci. Technol. 24(6): 1074-1085 (2009) - [j13]Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li:
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1173-1186 (2009) - [c37]Songwei Pei, Huawei Li, Xiaowei Li:
A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium 2009: 145-150 - [c36]Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu:
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium 2009: 219-224 - [c35]Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan:
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium 2009: 437-442 - [c34]Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang:
Impact of Hazards on Pattern Selection for Small Delay Defects. PRDC 2009: 49-54 - [c33]Li Liu, Jishun Kuang, Huawei Li:
Small Delay Fault Simulation for Sequential Circuits. PRDC 2009: 63-68 - [c32]Songwei Pei, Huawei Li, Xiaowei Li:
Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC 2009: 75-80 - [c31]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC 2009: 276-281 - [c30]Tao Lv, Huawei Li, Xiaowei Li:
Automatic Selection of Internal Observation Signals for Design Verification. VTS 2009: 203-208 - 2008
- [j12]Da Wang, Yu Hu, Huawei Li, Xiaowei Li:
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23(6): 1037-1046 (2008) - [c29]Fei Wang, Yu Hu, Huawei Li, Xiaowei Li:
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC 2008: 571-576 - [c28]Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li:
Robust test generation for power supply noise induced path delay faults. ASP-DAC 2008: 659-662 - [c27]Ying Zhang, Huawei Li, Xiaowei Li:
Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. ATS 2008: 438-443 - [c26]Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li:
A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA 2008: 326-331 - [c25]Minjin Zhang, Huawei Li, Xiaowei Li:
Static Crosstalk Noise Analysis with Transition Map. DELTA 2008: 462-465 - [c24]Hui Liu, Huawei Li, Yu Hu, Xiaowei Li:
A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA 2008: 521-526 - [c23]Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang:
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC 2008: 1-10 - [c22]Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu:
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS 2008: 377-382 - [c21]Minjin Zhang, Huawei Li, Xiaowei Li:
Multiple Coupling Effects Oriented Path Delay Test Generation. VTS 2008: 383-388 - 2007
- [j11]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 531-540 (2007) - [c20]Lei Zhang, Huawei Li, Xiaowei Li:
A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) 2007: 1210-1219 - [c19]Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li:
Bug analysis and corresponding error models in real designs. HLDVT 2007: 59-64 - [c18]Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li:
The design-for-testability features of a general purpose microprocessor. ITC 2007: 1-9 - 2006
- [j10]Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes. Sci. China Ser. F Inf. Sci. 49(2): 262-272 (2006) - [j9]Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Trans. Inf. Syst. 89-D(10): 2616-2625 (2006) - [j8]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE Trans. Instrum. Meas. 55(2): 389-399 (2006) - [c17]Tao Lv, Ling-Yi Liu, Yang Zhao, Huawei Li, Xiaowei Li:
An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. ATS 2006: 89-94 - [c16]Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han:
Fast Packet Classification using Group Bit Vector. GLOBECOM 2006 - [c15]Huawei Li, Pei-Fu Shen, Xiaowei Li:
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS 2006: 300-305 - 2005
- [j7]Huawei Li, Xiaowei Li:
Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electron. Test. 21(2): 181-195 (2005) - [j6]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. 88-D(9): 2126-2134 (2005) - [j5]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005) - [j4]Shuguang Gong, Huawei Li, Xiaowei Li:
An innovative free memory design for network processors in home network gateway. IEEE Trans. Consumer Electron. 51(4): 1182-1187 (2005) - [c14]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58 - [c13]Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li:
Design of an efficient memory subsystem for network processor. ASP-DAC 2005: 897-900 - [c12]Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li:
Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium 2005: 120-125 - [c11]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243 - [c10]Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen:
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 - 2004
- [c9]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 - [c8]Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 - [c7]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 - 2003
- [j3]Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li:
A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. 18(3): 308-317 (2003) - [c6]Huawei Li, Yue Zhang, Xiaowei Li:
Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium 2003: 178-183 - [c5]Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445 - 2002
- [j2]Huawei Li, Yinghua Min, Zhongcheng Li:
Clustering of behavioral phases in FSMs and its applications to VLSI test. Sci. China Ser. F Inf. Sci. 45(6): 462-478 (2002) - [c4]Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min:
Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium 2002: 332-337 - 2001
- [c3]Huawei Li, Yinghua Min, Zhongcheng Li:
An RT-Level ATPG Based on Clustering of Circuit States. Asian Test Symposium 2001: 213-218 - [c2]Xiaowei Li, Huawei Li, Yinghua Min:
Reducing Power Dissipation during At-Speed Test Application. DFT 2001: 116- - 2000
- [j1]Huawei Li, Zhongcheng Li, Yinghua Min:
Reduction of Number of Paths to be Tested in Delay Testing. J. Electron. Test. 16(5): 477-485 (2000)
1990 – 1999
- 1998
- [c1]Huawei Li, Zhongcheng Li, Yinghua Min:
Delay Testing with Double Observations. Asian Test Symposium 1998: 96-
Coauthor Index
[j90] [c188] [c183] [c182] [c181] [c179] [i28] [i27] [c166] [c160] [i19] [c152] [j57] [c136] [c114] [c113] [j50] [j49] [c101] [j44] [j42] [j36] [j35] [j34] [c83] [c82] [c80] [j32] [j31] [c70] [c69] [c66] [c64] [j30] [j28] [j26] [c62] [c60] [j25] [c56] [j19] [j18] [c51] [c50] [c46] [c43] [c41] [c39] [j13] [c36] [c35] [c31] [j11] [j10] [j9] [j8] [c16] [j6] [j5] [c14] [c11] [c9] [c8] [c7] [c5]
[j93] [j91] [j90] [j89] [j88] [j86] [j85] [c188] [c186] [c185] [c184] [c183] [c182] [c181] [c179] [c178] [c177] [c176] [c175] [c174] [c173] [i28] [i26] [i25] [i24] [i23] [j84] [j83] [j82] [j81] [j80] [j79] [j78] [j77] [c172] [c170] [c168] [c167] [c165] [c163] [c162] [c160] [i21] [i20] [i19] [i18] [i16] [i15] [i13] [i12] [j76] [j75] [j74] [j73] [j72] [j71] [j69] [c157] [c155] [c154] [c153] [c152] [c151] [c150] [c149] [c148] [i9] [i8] [i7] [j66] [j65] [j64] [j62] [c147] [c146] [c145] [c144] [c142] [c141] [i6] [i5] [i4] [i3] [i2] [j61] [j60] [j57] [c139] [c138] [c137] [c136] [c132] [c131] [c130] [c128] [j55] [j54] [j53] [j52] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c115] [c114] [c113] [c112] [c111] [c109] [c107] [i1] [j49] [j48] [j47] [j46] [c106] [c105] [c103] [c101] [c99] [c98] [c95] [j44] [j42] [j41] [c94] [c90] [c89] [c88] [c86] [c85] [j40] [j39] [j38] [j37] [j35] [j34] [c84] [c83] [c82] [c81] [c78] [c76] [c75] [j33] [j32] [j31] [c73] [c72] [c71] [c70] [c69] [c67] [c66] [c65] [j28] [j27] [j26] [c63] [c61] [c60] [c59] [c58] [j25] [j24] [j23] [c57] [c56] [c55] [j22] [j21] [j20] [c54] [c53] [j19] [j18] [j17] [j16] [c52] [c51] [c50] [c49] [j15] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j14] [j13] [c37] [c35] [c34] [c32] [c31] [c30] [j12] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j11] [c20] [c19] [c18] [j10] [j9] [j8] [c17] [c16] [c15] [j7] [j6] [j5] [j4] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [j3] [c6] [c5] [c4] [c2]
[j90] [j89] [j88] [c188] [c186] [c183] [c182] [c181] [c179] [c178] [c177] [i28] [i27] [j83] [j81] [j79] [j78] [j77] [c170] [c166] [c162] [c160] [c158] [i21] [i20] [i19] [i18] [i16] [i15] [i12] [j76] [j75] [j74] [j73] [j72] [j71] [j69] [c155] [c154] [c153] [c152] [c151] [i7] [j66] [j65] [j64] [j63] [j62] [c146] [c145] [c144] [c142] [c141] [i6] [i5] [i4] [i3] [c140] [c137] [c136] [c135] [c133] [c131] [c130] [c129] [j54] [j53] [j52] [c126] [c125] [c124] [c122] [c121] [c120] [c119] [c118] [c117] [c111] [c109] [c107] [j49] [j48] [j47] [c105] [c101] [c100] [c99] [c98] [j44] [j42] [j41] [c94] [c91] [c89] [c88] [c86] [j35] [j34] [c83] [c82] [c81] [c78] [j32] [j31] [c73] [c72] [c71] [c70] [c69] [c67] [c66] [c65] [j30] [c62] [c60] [c56] [c51] [c39]
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