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2020 – today
- 2023
[i8]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. CoRR abs/2306.09552 (2023)- 2022
- [j6]Ardavan Pedram
, Ali Shafiee Ardestani, Ling Li, Hamzah Abdel-Aziz, Jun Fang, Joseph Hassoun:
Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators. J. Syst. Archit. 126: 102454 (2022) - [c17]Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun:
Griffin: Rethinking Sparse Optimization for Deep Learning Architectures. HPCA 2022: 861-875 - 2021
- [c16]Hamzah Abdel-Aziz, Ali Shafiee, Jong Hoon Shin, Ardavan Pedram, Joseph Hassoun:
Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators. MLSys 2021 - [i7]Hamzah Abdel-Aziz, Ali Shafiee, Jong Hoon Shin, Ardavan Pedram, Joseph H. Hassoun:
Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators. CoRR abs/2101.11748 (2021) - [i6]Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun:
Design Space Exploration of Sparse Accelerators for Deep Neural Networks. CoRR abs/2107.12922 (2021) - 2020
- [i5]Noah Gamboa, Kais Kudrolli, Anand Dhoot, Ardavan Pedram:
Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators. CoRR abs/2001.03253 (2020)
2010 – 2019
- 2018
- [j5]Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun:
Plasticine: A Reconfigurable Accelerator for Parallel Patterns. IEEE Micro 38(3): 20-31 (2018) - [c15]David Koeplinger, Matthew Feldman, Raghu Prabhakar, Yaqi Zhang, Stefan Hadjis, Ruben Fiszel, Tian Zhao, Luigi Nardi, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun:
Spatial: a language and compiler for application accelerators. PLDI 2018: 296-311 - 2017
- [j4]Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test 34(2): 39-50 (2017) - [c14]Yuanfang Li, Ardavan Pedram:
CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks. ASAP 2017: 1-10 - [c13]Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun:
Plasticine: A Reconfigurable Architecture For Parallel Paterns. ISCA 2017: 389-402 - [i4]Yuanfang Li, Ardavan Pedram:
CATERPILLAR: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks. CoRR abs/1706.00517 (2017) - 2016
- [c12]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally:
Deep compression and EIE: Efficient inference engine on compressed deep neural network. Hot Chips Symposium 2016: 1-6 - [c11]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
EIE: Efficient Inference Engine on Compressed Deep Neural Network. ISCA 2016: 243-254 - [c10]Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Improving energy efficiency of DRAM by exploiting half page row access. MICRO 2016: 27:1-27:12 - [c9]Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Evaluating programmable architectures for imaging and vision applications. MICRO 2016: 52:1-52:13 - [c8]Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer:
Simulator calibration for accelerator-rich architecture studies. SAMOS 2016: 88-95 - [i3]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
EIE: Efficient Inference Engine on Compressed Deep Neural Network. CoRR abs/1602.01528 (2016) - [i2]Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR abs/1602.04183 (2016) - [i1]Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz:
A Systematic Approach to Blocking Convolutional Neural Networks. CoRR abs/1606.04209 (2016) - 2014
- [j3]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator. IEEE Trans. Computers 63(8): 1854-1867 (2014) - [j2]Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer:
A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores. J. Signal Process. Syst. 77(1-2): 169-190 (2014) - 2013
- [c7]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
Floating Point Architecture Extensions for Optimized Matrix Factorization. IEEE Symposium on Computer Arithmetic 2013: 49-58 - [c6]Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer:
Transforming a linear algebra core to an FFT accelerator. ASAP 2013: 175-184 - [c5]Ardavan Pedram:
Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics. IPDPS Workshops 2013: 2214-2217 - 2012
- [j1]Ardavan Pedram, Robert A. van de Geijn, Andreas Gerstlauer:
Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures. IEEE Trans. Computers 61(12): 1724-1736 (2012) - [c4]Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert A. van de Geijn, Michael J. Schulte, Andreas Gerstlauer:
A Linear Algebra Core Design for Efficient Level-3 BLAS. ASAP 2012: 149-152 - [c3]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators. SBAC-PAD 2012: 19-26 - 2011
- [c2]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
A high-performance, low-power linear algebra core. ASAP 2011: 35-42
2000 – 2009
- 2009
- [c1]Ardavan Pedram, David Craven, Andreas Gerstlauer:
Modeling Cache Effects at the Transaction Level. IESS 2009: 89-101
Coauthor Index
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