default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSarma B. K. Vrudhula
Person information
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j60]Ankit Wagle, Gian Singh
, Sunil P. Khatri, Sarma B. K. Vrudhula:
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2057-2070 (2024)- [j59]Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1025-1038 (2024) - [c127]Gian Singh, Sarma B. K. Vrudhula:
A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. ACM Great Lakes Symposium on VLSI 2024: 57-62 - [c126]Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria:
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA 2024: 671-685 - [c125]Gian Singh, Ayushi Dube, Sarma B. K. Vrudhula:
Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture. ISVLSI 2024: 186-191 - [c124]Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu:
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. MLSys 2024 - [c123]Gian Singh, Ayushi Dube, Sarma B. K. Vrudhula:
A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. VLSI-SoC 2024: 1-6 - [i11]Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu:
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. CoRR abs/2403.04207 (2024) - 2023
- [j58]Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula:
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4164-4176 (2023) - [c122]Gian Singh, Sanmukh R. Kuppannagari, Sarma B. K. Vrudhula:
PARAG: PIM Architecture for Real-Time Acceleration of GCNs. HiPC 2023: 11-20 - [c121]Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. ISQED 2023: 1-7 - [i10]Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma B. K. Vrudhula, Sachin S. Sapatnekar:
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR abs/2306.09434 (2023) - 2022
- [j57]Soroush Heidari, Mehdi Ghasemi, Young Geun Kim, Carole-Jean Wu, Sarma B. K. Vrudhula:
CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs. IEEE Trans. Computers 71(12): 3191-3202 (2022) - [j56]Ankit Wagle, Sarma B. K. Vrudhula:
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1855-1867 (2022) - [j55]Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2968-2981 (2022) - [j54]Mehdi Ghasemi, Daler N. Rakhmatov, Carole-Jean Wu, Sarma B. K. Vrudhula:
EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays. ACM Trans. Embed. Comput. Syst. 21(5): 66:1-66:27 (2022) - [c120]Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Flash-based Current-mode IC to Realize Quantized Neural Networks. DATE 2022: 1029-1034 - [c119]Ayushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula:
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. ICCAD 2022: 151:1-151:9 - [i9]Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. CoRR abs/2204.08070 (2022) - 2021
- [c118]Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri:
CIDAN: Computing in DRAM with Artificial Neurons. ICCD 2021: 349-356 - [c117]Mehdi Ghasemi, Soroush Heidari, Young Geun Kim, Aaron Lamb, Carole-Jean Wu, Sarma B. K. Vrudhula:
Energy-Efficient Mapping for a Network of DNN Models at the Edge. SMARTCOMP 2021: 25-30 - [i8]Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. CoRR abs/2104.01699 (2021) - [i7]Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri:
CIDAN: Computing in DRAM with Artificial Neurons. CoRR abs/2112.00117 (2021) - 2020
- [j53]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 424-437 (2020) - [j52]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 843-856 (2020) - [j51]Elham Azari, Sarma B. K. Vrudhula:
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. ACM Trans. Embed. Comput. Syst. 19(1): 3:1-3:21 (2020) - [c116]Mohammad Farhadi, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang:
Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CVPR Workshops 2020: 1591-1599 - [c115]Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ICCD 2020: 433-440 - [c114]Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. ISQED 2020: 141-148 - [i6]Mohammad Farhadi Bajestani, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang:
Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CoRR abs/2004.05746 (2020)
2010 – 2019
- 2019
- [j50]Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula:
Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties. IEEE Trans. Mob. Comput. 18(12): 2941-2953 (2019) - [c113]Elham Azari, Sarma B. K. Vrudhula:
An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing. IEEE BigData 2019: 4450-4459 - [c112]Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula:
An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. FPGA 2019: 305-306 - [c111]Ankit Wagle, Elham Azari, Sarma B. K. Vrudhula:
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. ICCAD 2019: 1-8 - [c110]Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula:
Threshold Logic in a Flash. ICCD 2019: 550-558 - [i5]Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula:
Threshold Logic in a Flash. CoRR abs/1910.04910 (2019) - [i4]Elham Azari, Sarma B. K. Vrudhula:
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. CoRR abs/1910.08683 (2019) - 2018
- [j49]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [j48]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1354-1367 (2018) - [j47]Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2628-2640 (2018) - [c109]Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. FPL 2018: 256-259 - [c108]Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD 2018: 57 - [c107]Davesh Shingari, Akhil Arunkumar, Benjamin Gaudette, Sarma B. K. Vrudhula, Carole-Jean Wu:
DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference. ISPASS 2018: 64-75 - 2017
- [c106]Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula:
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. DAC 2017: 67:1-67:6 - [c105]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54 - [c104]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL 2017: 1-8 - [c103]Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS 2017: 1-4 - [c102]Mehmet Ince, Sule Ozev, Sarma B. K. Vrudhula:
Statistical library characterization using arbitrary polynomial chaos. LASCAS 2017: 1-4 - 2016
- [j46]Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula:
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2873-2886 (2016) - [c101]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c100]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - [c99]Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula:
Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee. HPCA 2016: 52-63 - [c98]Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - [c97]Debayan Mahalanabis, M. Sivaraj, W. Chen, S. Shah, Hugh J. Barnaby, Michael N. Kozicki, Jennifer Blain Christen, Sarma B. K. Vrudhula:
Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons. ISCAS 2016: 2314-2317 - [c96]Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Digital IP protection using threshold voltage control. ISQED 2016: 344-349 - [i3]Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Digital IP Protection Using Threshold Voltage Control. CoRR abs/1603.07370 (2016) - [i2]Niranjan Kulkarni, Sarma B. K. Vrudhula:
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. CoRR abs/1603.07371 (2016) - 2015
- [j45]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [j44]Debayan Mahalanabis, Vineeth Bharadwaj, Hugh J. Barnaby, Sarma B. K. Vrudhula, Michael N. Kozicki:
A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 205-213 (2015) - [j43]Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula:
Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems 39(8): 807-815 (2015) - [c95]Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula:
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC 2015: 1-4 - [c94]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c93]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - [c92]Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD 2015: 443-446 - [c91]Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang:
Design of threshold logic gates using emerging devices. ISCAS 2015: 373-376 - [c90]Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula:
Fast and robust differential flipflops and their extension to multi-input threshold gates. ISCAS 2015: 822-825 - 2014
- [j42]Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao:
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae 134(1-2): 183-200 (2014) - [j41]Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula:
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. J. Parallel Distributed Comput. 74(6): 2452-2460 (2014) - [j40]Vinay Hanumaiah, Sarma B. K. Vrudhula:
Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling. IEEE Trans. Computers 63(2): 349-360 (2014) - [j39]Vinay Hanumaiah, Digant Desai, Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula:
STEAM: A Smart Temperature and Energy Aware Multicore Controller. ACM Trans. Embed. Comput. Syst. 13(5s): 151:1-151:25 (2014) - [j38]Benjamin Gaudette, Vinay Hanumaiah, Marwan Krunz, Sarma B. K. Vrudhula:
Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks. ACM Trans. Sens. Networks 10(4): 59:1-59:27 (2014) - [c89]Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao:
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c88]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539 - [c87]Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
Branch-Aware Loop Mapping on CGRAs. DAC 2014: 107:1-107:6 - [c86]Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula:
A fast, energy efficient, field programmable threshold-logic array. FPT 2014: 300-305 - [c85]Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula:
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH 2014: 39-44 - 2013
- [c84]Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). DAC 2013: 18:1-18:10 - 2012
- [j37]Vinay Hanumaiah, Sarma B. K. Vrudhula:
Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors. IEEE Trans. Computers 61(10): 1484-1494 (2012) - [c83]Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
EPIMap: using epimorphism to map applications on CGRAs. DAC 2012: 1284-1291 - [c82]Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula:
Minimizing area and power of sequential CMOS circuits using threshold decomposition. ICCAD 2012: 605-612 - [c81]Benjamin Gaudette, Vinay Hanumaiah, Sarma B. K. Vrudhula, Marwan Krunz:
Optimal range assignment in solar powered active wireless sensor networks. INFOCOM 2012: 2354-2362 - [c80]Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula:
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. NANOARCH 2012: 188-195 - 2011
- [j36]Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski:
Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 665-677 (2011) - [j35]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1677-1690 (2011) - [c79]Vinay Hanumaiah, Sarma B. K. Vrudhula:
Reliability-aware thermal management for hard real-time applications on multi-core processors. DATE 2011: 137-142 - [c78]Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula:
A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation. ACM Great Lakes Symposium on VLSI 2011: 139-144 - [c77]Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula:
Enabling Multithreading on CGRAs. ICPP 2011: 255-264 - [c76]Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula:
Temperature dependent wire delay estimation in floorplanning. NORCHIP 2011: 1-4 - 2010
- [j34]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 173-183 (2010) - [j33]Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 988-997 (2010) - [c75]Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula:
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI 2010: 210-215
2000 – 2009
- 2009
- [j32]Ravishankar Rao, Sarma B. K. Vrudhula:
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1559-1572 (2009) - [j31]Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang, Sarma B. K. Vrudhula:
Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 22-32 (2009) - [c74]Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula:
A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362 - [c73]Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha:
Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781 - [c72]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Performance optimal speed control of multi-core processors under thermal constraints. DATE 2009: 1548-1551 - [c71]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD 2009: 310-313 - 2008
- [j30]Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula:
Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. 2(4): 361-371 (2008) - [j29]Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electron. 4(1): 68-80 (2008) - [j28]Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 445-455 (2008) - [j27]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel:
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1812-1825 (2008) - [j26]Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula:
A fuel-cell-battery hybrid for portable embedded systems. ACM Trans. Design Autom. Electr. Syst. 13(1): 19:1-19:34 (2008) - [c70]Tejaswi Gowda, Sarma B. K. Vrudhula:
Decomposition based approach for synthesis of multi-level threshold logic circuits. ASP-DAC 2008: 125-130 - [c69]Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Seungchan Kim:
Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. BIODEVICES (1) 2008: 212-219 - [c68]Amit Goel, Sarma B. K. Vrudhula:
Statistical waveform and current source based standard cell models for accurate timing analysis. DAC 2008: 227-230 - [c67]Amit Goel, Sarma B. K. Vrudhula:
Current source based standard cell model for accurate signal integrity and timing analysis. DATE 2008: 574-579 - [c66]Ravishankar Rao, Sarma B. K. Vrudhula:
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. ICCAD 2008: 537-542 - [c65]Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski:
Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED 2008: 229-232 - [c64]Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula:
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. ISQED 2008: 123-126 - [c63]Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta:
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. ISQED 2008: 200-206 - [c62]Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520 - [c61]Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539 - 2007
- [j25]Praveen Ghanta, Sarma B. K. Vrudhula:
Analysis of Power Supply Noise in the Presence of Process Variations. IEEE Des. Test Comput. 24(3): 256-266 (2007) - [j24]Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. J. Multiple Valued Log. Soft Comput. 13(4-6): 447-466 (2007) - [j23]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimal speed control of a producer-consumer device pair. ACM Trans. Embed. Comput. Syst. 6(4): 30 (2007) - [c60]Ravishankar Rao, Sarma B. K. Vrudhula:
Performance optimal processor throttling under thermal constraints. CASES 2007: 257-266 - [c59]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC 2007: 364-369 - [c58]Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Goran Konjevod:
Synthesis of threshold logic circuits using tree matching. ECCTD 2007: 850-853 - [c57]Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod:
Combinational equivalence checking for threshold logic circuits. ACM Great Lakes Symposium on VLSI 2007: 102-107 - [c56]Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti:
Throughput of multi-core processors under thermal constraints. ISLPED 2007: 201-206 - [c55]Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. ISMVL 2007: 24 - [c54]Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS 2007: 125-137 - [c53]Sarma B. K. Vrudhula, Sarvesh Bhardwaj:
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design 2007: 9 - [c52]Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design 2007: 589-594 - [i1]Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang:
Stochastic Power Grid Analysis Considering Process Variations. CoRR abs/0710.4649 (2007) - 2006
- [j22]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. 2(2): 240-250 (2006) - [j21]Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta:
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2001-2011 (2006) - [j20]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy-Optimal Speed Control of a Generic Device. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2737-2746 (2006) - [j19]Kaviraj Chopra, Sarma B. K. Vrudhula:
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2820-2832 (2006) - [j18]Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula:
Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. IEEE Trans. Wirel. Commun. 5(11): 3109-3118 (2006) - [c51]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC 2006: 953-958 - [c50]Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula:
Predictive Modeling of the NBTI Effect for Reliable Design. CICC 2006: 189-192 - [c49]Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda:
Stochastic variational analysis of large power grids considering intra-die correlations. DAC 2006: 211-216 - [c48]Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula:
Extending the lifetime of fuel cell based hybrid systems. DAC 2006: 562-567 - [c47]Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula:
High-level power management of embedded systems with application-specific energy cost functions. DAC 2006: 568-573 - [c46]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao:
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC 2006: 791-796 - [c45]Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
A framework for statistical timing analysis using non-linear delay and slew models. ICCAD 2006: 225-230 - [c44]Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang:
An optimal analytical solution for processor speed control with thermal constraints. ISLPED 2006: 292-297 - [c43]Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula:
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. ISLPED 2006: 424-429 - [c42]Praveen Ghanta, Sarma B. K. Vrudhula:
Variational Interconnect Delay Metrics for Statistical Timing Analysis. ISQED 2006: 19-24 - [c41]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED 2006: 717-722 - 2005
- [j17]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1784-1794 (2005) - [c40]Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC 2005: 541-546 - [c39]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimal speed control of devices with discrete speed sets. DAC 2005: 901-904 - [c38]Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang:
Stochastic Power Grid Analysis Considering Process Variations. DATE 2005: 964-969 - [c37]Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. DSD 2005: 139-143 - [c36]Ravishankar Rao, Sarma B. K. Vrudhula:
Battery optimization vs energy optimization: which to choose and when? ICCAD 2005: 439-445 - [c35]Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD 2005: 713-718 - [c34]Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula:
Power balanced coverage-time optimization for clustered wireless sensor networks. MobiHoc 2005: 111-120 - 2004
- [c33]Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan:
Disk drive energy optimization for audio-video applications. CASES 2004: 93-103 - [c32]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 - [c31]Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang:
A methodology to improve timing yield in the presence of process variations. DAC 2004: 448-453 - [c30]Kaviraj Chopra, Sarma B. K. Vrudhula:
Implicit pseudo boolean enumeration algorithms for input vector control. DAC 2004: 767-772 - [c29]Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan:
A Framework for Battery-Aware Sensor Management. DATE 2004: 962-967 - [c28]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimization for a two-device data flow chain. ICCAD 2004: 268-274 - [c27]Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula:
Stochastic analysis of interconnect performance in the presence of process variations. ICCAD 2004: 880-886 - [c26]Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj:
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240- - [c25]Raghukiran Sreeramaneni, Sarma B. K. Vrudhula:
Energy Profiler for Hardware/Software Co-Design. VLSI Design 2004: 335- - 2003
- [j16]Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov:
Battery Modeling for Energy-Aware System Design. Computer 36(12): 77-87 (2003) - [j15]Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Probabilistic analysis of interconnect coupling noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1188-1203 (2003) - [j14]Daler N. Rakhmatov, Sarma B. K. Vrudhula:
Energy management for battery-powered embedded systems. ACM Trans. Embed. Comput. Syst. 2(3): 277-324 (2003) - [j13]Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach:
A model for battery lifetime analysis for organizing applications on a pocket computer. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1019-1030 (2003) - [c24]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353 - [c23]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067 - [c22]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620 - [c21]Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov:
Analysis of discharge techniques for multiple battery systems. ISLPED 2003: 44-47 - 2002
- [j12]Qi Wang, Sarma B. K. Vrudhula:
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 306-318 (2002) - [j11]Haibo Wang, Sarma B. K. Vrudhula:
Behavioral synthesis of field programmable analog array circuits. ACM Trans. Design Autom. Electr. Syst. 7(4): 563-604 (2002) - [c20]Daler N. Rakhmatov, Sarma B. K. Vrudhula:
Hardware-software bipartitioning for dynamically reconfigurable systems. CODES 2002: 145-150 - [c19]Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti:
Battery-conscious task sequencing for portable devices including voltage/clock scaling. DAC 2002: 189-194 - [c18]Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658 - [c17]Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422 - [c16]Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach:
Battery lifetime prediction for energy-aware computing. ISLPED 2002: 154-159 - [c15]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21 - [c14]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36 - 2001
- [c13]Daler N. Rakhmatov, Sarma B. K. Vrudhula:
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. ICCAD 2001: 488-493 - [c12]Daler N. Rakhmatov, Sarma B. K. Vrudhula:
Minimizing routing configuration cost in dynamically reconfigurable FPGAs. IPDPS 2001: 145 - [c11]Daler N. Rakhmatov, Sarma B. K. Vrudhula:
Time-to-failure estimation for batteries in portable electronic systems. ISLPED 2001: 88-91 - 2000
- [j10]Daler N. Rakhmatov, Sarma B. K. Vrudhula, Thomas J. Brown, Ajay Nagarandal:
Adaptive Multiuser Online Reconfigurable Engine. IEEE Des. Test Comput. 17(1): 53-67 (2000)
1990 – 1999
- 1999
- [j9]Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly:
Power reduction and power-delay trade-offs using logic transformations. ACM Trans. Design Autom. Electr. Syst. 4(1): 97-121 (1999) - [c10]Qi Wang, Sarma B. K. Vrudhula:
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. ICCD 1999: 556-562 - 1998
- [j8]Hong-Yu Xie, Sarma B. K. Vrudhula:
A Technique for Estimating Signal Activity in Logic Circuits. Integr. Comput. Aided Eng. 5(2): 141-152 (1998) - [c9]Qi Wang, Sarma B. K. Vrudhula:
Data Driven Power Optimization of Sequential Circuits. DATE 1998: 686-691 - [c8]Qi Wang, Sarma B. K. Vrudhula:
Static power optimization of deep submicron CMOS circuits for dual VT technology. ICCAD 1998: 490-496 - [c7]Qi Wang, Sarma B. K. Vrudhula:
On short circuit power estimation of CMOS inverters. ICCD 1998: 70-75 - 1997
- [c6]Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly:
An Investigation of Power Delay Trade-Offs on PowerPC Circuits. DAC 1997: 425-428 - [c5]K. McCarley, Sarma B. K. Vrudhula:
Macro-instruction generation for dynamic logic caching. IEEE International Workshop on Rapid System Prototyping 1997: 63-69 - [c4]E. Tsun, Sarma B. K. Vrudhula:
Rapid prototyping of networks of asynchronous multiple functional units. IEEE International Workshop on Rapid System Prototyping 1997: 157-166 - 1996
- [j7]Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
Formal Verification Using Edge-Valued Binary Decision Diagrams. IEEE Trans. Computers 45(2): 247-255 (1996) - [c3]Qi Wang, Sarma B. K. Vrudhula:
Multi-level logic optimization for low power using local logic transformations. ICCAD 1996: 270-277 - 1995
- [j6]Amitava Majumdar, Sarma B. K. Vrudhula:
Fault Coverage and Test Length Estimation for Random Pattern Testing. IEEE Trans. Computers 44(2): 234-247 (1995) - 1994
- [j5]Amitava Majumdar, Sarma B. K. Vrudhula:
Techniques for estimating test length under random test. J. Electron. Test. 5(2-3): 285-297 (1994) - [j4]Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 959-975 (1994) - [j3]King C. Ho, Sarma B. K. Vrudhula:
Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1201-1222 (1994) - 1993
- [j2]T.-Y. Wuu, Sarma B. K. Vrudhula:
A design of a fast and area efficient multi-input Muller C-element. IEEE Trans. Very Large Scale Integr. Syst. 1(2): 215-219 (1993) - [j1]Amitava Majumdar, Sarma B. K. Vrudhula:
Analysis of signal probability in logic circuits using stochastic models. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 365-379 (1993) - [c2]Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. DAC 1993: 642-647 - [c1]Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
FGILP: an integer linear program solver based on function graphs. ICCAD 1993: 685-689
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-11 21:40 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
