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2020 – today
- 2024
[j10]Amr I. Eissa
, Enrique Alvarez-Fontecilla, Colin Weltin-Wu, Ian Galton:
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4524-4537 (2024)- 2021
- [j9]Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton:
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 965-974 (2021)
2010 – 2019
- 2019
- [j8]Ian Galton, Colin Weltin-Wu:
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 1-19 (2019) - 2015
- [j7]Colin Weltin-Wu, Guobi Zhao, Ian Galton:
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. IEEE J. Solid State Circuits 50(12): 2988-3002 (2015) - [j6]Colin Weltin-Wu, Eythan Familier, Ian Galton:
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2013-2023 (2015) - [c6]Colin Weltin-Wu, Guobi Zhao, Ian Galton:
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. ISSCC 2015: 1-3 - 2013
- [j5]Colin Weltin-Wu, Yannis P. Tsividis:
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution. IEEE J. Solid State Circuits 48(9): 2180-2190 (2013) - 2012
- [j4]Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis:
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation. IEEE J. Solid State Circuits 47(9): 2164-2173 (2012) - [c5]Colin Weltin-Wu, Yannis P. Tsividis:
An event-driven, alias-free ADC with signal-dependent resolution. VLSIC 2012: 28-29 - 2011
- [c4]Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis:
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity. ISSCC 2011: 232-234 - 2010
- [j3]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto:
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. IEEE J. Solid State Circuits 45(12): 2723-2736 (2010) - [j2]Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto:
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2259-2268 (2010) - [c3]Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto:
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. ISSCC 2010: 468-469
2000 – 2009
- 2009
- [j1]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. IEEE J. Solid State Circuits 44(3): 824-834 (2009) - [c2]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
Insights into wideband fractional All-Digital PLLs for RF applications. CICC 2009: 37-44 - 2008
- [c1]Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto:
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. ISSCC 2008: 344-345
Coauthor Index
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