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ORCIDAsit K. Mishra
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- affiliation: Penn State, University Park, USA
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2020 – today
- 2021
[i8]Asit K. Mishra, Jorge Albericio Latorre, Jeff Pool, Darko Stosic, Dusan Stosic, Ganesh Venkatesh, Chong Yu, Paulius Micikevicius:
Accelerating Sparse Deep Neural Networks. CoRR abs/2104.08378 (2021)- [i7]Anup Sarma, Sonali Singh, Huaipan Jiang, Ashutosh Pattnaik, Asit K. Mishra, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Chita R. Das:
Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs. CoRR abs/2109.07710 (2021)
2010 – 2019
- 2019
- [c37]Ashutosh Pattnaik, Xulong Tang
, Onur Kayiran, Adwait Jog, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das:
Opportunistic computing in GPU architectures. ISCA 2019: 210-223 - 2018
- [c36]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM 2018: 73-80 - [c35]Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA 2018: 107-116 - [c34]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA 2018: 287 - [c33]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA 2018: 294 - [c32]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL 2018: 106-110 - [c31]Asit K. Mishra, Debbie Marr:
Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. ICLR (Poster) 2018 - [c30]Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr:
WRPN: Wide Reduced-Precision Networks. ICLR (Poster) 2018 - [i6]Asit K. Mishra, Debbie Marr:
WRPN & Apprentice: Methods for Training and Inference using Low-Precision Numerics. CoRR abs/1803.00227 (2018) - [i5]Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR abs/1806.11547 (2018) - 2017
- [c29]Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr:
Fine-grained accelerators for sparse machine learning workloads. ASP-DAC 2017: 635-640 - [c28]Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
High performance binary neural networks on the Xeon+FPGA™ platform. FPL 2017: 1-4 - [i4]Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr:
WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR abs/1704.03079 (2017) - [i3]Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr:
WRPN: Wide Reduced-Precision Networks. CoRR abs/1709.01134 (2017) - [i2]Supriya Kapur, Asit K. Mishra, Debbie Marr:
Low Precision RNNs: Quantizing RNNs Without Losing Accuracy. CoRR abs/1710.07706 (2017) - [i1]Asit K. Mishra, Debbie Marr:
Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. CoRR abs/1711.05852 (2017) - 2016
- [c27]Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Chita R. Das:
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities. PACT 2016: 31-44 - [c26]Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr:
Hardware accelerator for analytics of sparse data. DATE 2016: 1616-1621 - [c25]Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr:
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL 2016: 1-4 - [c24]Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr:
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT 2016: 77-84 - [c23]Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra:
ScalCore: Designing a core for voltage scalability. HPCA 2016: 681-693 - 2015
- [c22]Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr:
A sparse matrix vector multiply accelerator for support vector machine. CASES 2015: 109-116 - 2014
- [c21]Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas:
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. HPCA 2014: 440-451 - 2013
- [c20]Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das:
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance. ASPLOS 2013: 395-406 - [c19]Asit K. Mishra, Onur Mutlu, Chita R. Das:
A heterogeneous multiple network-on-chip design: an application-aware approach. DAC 2013: 36:1-36:10 - [c18]Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu:
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA 2013: 198-209 - [c17]Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das:
Orchestrated scheduling and prefetching for GPGPUs. ISCA 2013: 332-343 - 2012
- [c16]Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das:
PEPON: performance-aware hierarchical power budgeting for NoC based multicores. PACT 2012: 65-74 - [c15]Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das:
Application-aware prefetch prioritization in on-chip networks. PACT 2012: 441-442 - [c14]Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das:
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC 2012: 243-252 - 2011
- [j3]Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan:
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 109-119 (2011) - [j2]Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71(5): 625-640 (2011) - [c13]Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan:
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. DAC 2011: 729-734 - [c12]Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das:
ACCESS: Smart scheduling for asymmetric cache CMPs. HPCA 2011: 527-538 - [c11]Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80 - [c10]Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das:
A case for heterogeneous on-chip interconnects for CMPs. ISCA 2011: 389-400 - [c9]Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das:
METE: meeting end-to-end QoS in multicores through system-wide resource management. SIGMETRICS 2011: 13-24 - 2010
- [j1]Asit K. Mishra, Joseph L. Hellerstein, Walfredo Cirne, Chita R. Das:
Towards characterizing cloud backend workloads: insights from Google compute clusters. SIGMETRICS Perform. Evaluation Rev. 37(4): 34-41 (2010) - [c8]Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das:
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. SC 2010: 1-12 - [c7]Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das:
Coordinated power management of voltage islands in CMPs. SIGMETRICS 2010: 359-360
2000 – 2009
- 2009
- [c6]Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das:
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186 - [c5]Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303 - [c4]Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir:
A case for integrated processor-cache partitioning in chip multiprocessors. SC 2009 - 2008
- [c3]Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das:
Performance and power optimization through data compression in Network-on-Chip architectures. HPCA 2008: 215-225 - [c2]Asit K. Mishra, Aurobinda Routray, Ashok Kumar Pradhan:
Detection of Arcing in Low Voltage Distribution Systems. ICIIS 2008: 1-3 - [c1]Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261
Coauthor Index
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