default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMarc Renaudin
Person information
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2020
[c85]Radu Mateescu, Wendelin Serwe, Aymane Bouzafour, Marc Renaudin:
Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. MARS@ETAPS 2020: 200-239
2010 – 2019
- 2018
- [j18]Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson:
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. J. Low Power Electron. 14(3): 404-413 (2018) - [c84]Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe:
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC 2018: 34-42 - 2014
- [j17]Saeed Mian Qaisar
, Laurent Fesquet, Marc Renaudin:
Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. 94: 620-630 (2014) - [c83]Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels:
Clockless Design Performance Monitoring for Nanometer Technologies. ASYNC 2014: 108-109 - 2013
- [c82]Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin:
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC 2013: 67-74 - [c81]Alex Yakovlev, Pascal Vivet, Marc Renaudin:
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. DATE 2013: 1715-1724 - 2012
- [c80]Marc Renaudin, Alain Fonkoua:
Tiempo Asynchronous Circuits System Verilog Modeling Language. ASYNC 2012: 105-112 - 2011
- [j16]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin:
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24(2): 247-268 (2011) - [j15]Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard:
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. 16(3): 35:1-35:17 (2011) - [i3]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011) - 2010
- [j14]Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. 50(9-11): 1241-1246 (2010) - [c79]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP 2010: 115-122 - [c78]Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS 2010: 251 - [c77]Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Evaluating transient-fault effects on traditional C-element's implementations. IOLTS 2010: 35-40 - [c76]Marc Renaudin:
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. PATMOS 2010: 253
2000 – 2009
- 2009
- [j13]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Signal Process. 2009 (2009) - [j12]Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin:
Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 907-919 (2009) - [c75]Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin:
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC 2009: 3-12 - [c74]Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Comparing transient-fault effects on synchronous and on asynchronous circuits. IOLTS 2009: 29-34 - [c73]Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard:
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED 2009: 225-230 - [c72]Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin:
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS 2009: 327-332 - 2008
- [j11]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. J. Electr. Comput. Eng. 2008 (2008) - [c71]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - [c70]Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin:
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ASYNC 2008: 29-38 - [c69]Eslam Yahya, Marc Renaudin:
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. ICECS 2008: 1285-1289 - [c68]Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle:
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS 2008: 289-294 - 2007
- [j10]Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon:
Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distributed Syst. 18(1): 44-56 (2007) - [j9]J. Fragoso, Gilles Sicard, Marc Renaudin:
Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Tech. Sci. Informatiques 26(5): 535-565 (2007) - [c67]Estelle Labonne, Gilles Sicard, Marc Renaudin:
An on-pixel FPN reduction method for a high dynamic range CMO S imager. ESSCIRC 2007: 332-335 - [c66]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Computationally efficient adaptive rate sampling and filtering. EUSIPCO 2007: 2139-2143 - [c65]Cedric Koch-Hofer, Marc Renaudin:
Timed Asynchronous Circuits Modeling using SystemC. FDL 2007: 110-115 - [c64]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst:
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 - [c63]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. ICASSP (3) 2007: 1465-1468 - [c62]Eslam Yahya, Marc Renaudin:
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. ICECS 2007: 1288-1291 - [c61]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120 - [c60]Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet:
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS 2007: 295-306 - [c59]Sylvain Miermont, Pascal Vivet, Marc Renaudin:
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS 2007: 556-565 - [c58]Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois:
The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON 2007: 590-599 - [c57]Julien Goulier, Eric André, Marc Renaudin:
A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC (Selected Papers) 2007: 1-16 - [c56]Julien Goulier, Eric André, Marc Renaudin:
A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC 2007: 110-115 - [i2]G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain:
DPA on quasi delay insensitive asynchronous circuits: formalization and improvement. CoRR abs/0710.3443 (2007) - [i1]N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. CoRR abs/0710.4711 (2007) - 2006
- [j8]David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin:
On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electron. 2(1): 45-55 (2006) - [j7]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006) - [c55]D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin:
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC 2006: 86-97 - [c54]G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES 2006: 384-398 - [c53]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Spectral analysis of a signal driven sampling scheme. EUSIPCO 2006: 1-5 - [c52]Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel:
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97 - [c51]Estelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger:
A 100dB dynamic range CMOS image sensor with global shutter. ICECS 2006: 1133-1136 - [c50]Marc Renaudin, Yannick Monnet:
Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS 2006: 92-95 - [c49]Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet:
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130 - [c48]Eslam Yahya, Marc Renaudin:
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS 2006: 583-592 - [c47]Laurent Fesquet, Bertrand Folco, Mathieu Steiner, Marc Renaudin:
State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17 - [c46]Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin:
Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186 - 2005
- [c45]Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin:
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC 2005: 54-63 - [c44]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868 - [c43]N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33 - [c42]G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain:
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE 2005: 424-429 - [c41]G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain:
A clock-less low-voltage AES crypto-processor. ESSCIRC 2005: 403-406 - [c40]Yasser Ammar, Aurélien Buhrig, Marcin Marzencki, Benoît Charlot, Skandar Basrour, Karine Matou, Marc Renaudin:
Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator. sOc-EUSAI 2005: 287-292 - [c39]Laurent Fesquet, Marc Renaudin:
A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298 - [c38]Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin:
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304 - [c37]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134 - [c36]Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin:
A 120nm low power asynchronous ADC. ISLPED 2005: 60-65 - [c35]Aurélien Buhrig, Marc Renaudin, Dominique Barthel:
Asynchrnous Architecture for Sensor Network Nodes. Med-Hoc-Net 2005: 275-284 - [c34]David Rios-Arambula, Aurélien Buhrig, Marc Renaudin:
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS 2005: 10-18 - [c33]Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine:
A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580 - [c32]Laurent Fesquet, Jerome Quartana, Marc Renaudin:
Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112 - [c31]G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard:
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24 - [c30]Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin:
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69 - [c29]Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207 - 2004
- [j6]Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin:
La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Ann. des Télécommunications 59(7-8): 984-997 (2004) - [j5]Dhanistha Panyasak, Gilles Sicard, Marc Renaudin:
A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectron. J. 35(6): 531-540 (2004) - [c28]F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin:
Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206 - [c27]Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain:
High Security Smartcards. DATE 2004: 228-233 - [c26]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128 - [c25]Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin:
TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS 2004: 268-277 - 2003
- [c24]Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin:
A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205 - [c23]Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani:
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279 - [c22]João Leonardo Fragoso, Gilles Sicard, Marc Renaudin:
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS 2003: 171-180 - [c21]Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191 - [c20]João Leonardo Fragoso, Gilles Sicard, Marc Renaudin:
Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI 2003: 149-154 - [c19]Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
Validation of Asynchronous Circuit Specifications Using IF/CADP. VLSI-SoC (Selected Papers) 2003: 85-100 - [c18]Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91 - 2002
- [c17]Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090 - [c16]Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland:
Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46 - [c15]Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon:
Watershed parallel algorithm for asynchronous processors array. ICME (1) 2002: 793-796 - [c14]Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196 - [c13]Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard:
Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91 - [c12]Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin:
Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399 - 2001
- [j4]André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet:
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE J. Solid State Circuits 36(7): 1101-1107 (2001) - [c11]Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés:
Low-power systems on chips (SOCs). DATE 2001: 488 - [c10]Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1990 – 1999
- 1999
- [c9]Marc Renaudin, Pascal Vivet, Frédéric Robin:
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC 1999: 135-144 - 1998
- [c8]Marc Renaudin, Pascal Vivet, Frédéric Robin:
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC 1998: 22-31 - 1997
- [j3]Frédéric Robin, Gilles Privat, Marc Renaudin:
Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. Int. J. Pattern Recognit. Artif. Intell. 11(7): 1085-1094 (1997) - 1996
- [j2]Marc Renaudin, Bachar El-Hassan, Alain Guyot:
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider. IEEE J. Solid State Circuits 31(7): 1001-1013 (1996) - [c7]Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin:
Asynchronous SRT Dividers: The Real Cost. ED&TC 1996: 195-199 - [c6]Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering:
Self timed division and square-root extraction. VLSI Design 1996: 376-381 - 1995
- [c5]Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El-Hassan:
A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. ISCAS 1995: 1041-1044 - 1994
- [c4]Marc Renaudin, Bachar El-Hassan:
The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. ISCAS 1994: 291-294 - 1993
- [j1]A. K. Betts, Ivo Bolsens, Etienne Sicard, Marc Renaudin, Adrian Johnstone:
SMILE: A scalable microcontroller library element. Microprocess. Microprogramming 39(2-5): 259-262 (1993) - [c3]Patricia Planet, Gilles Privat, Marc Renaudin:
Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms. ASAP 1993: 156-159 - [c2]Michel Poize, Marc Renaudin, Patrick Venier:
A general time domain approach for the design of perfect reconstruction modulated filter banks. ICASSP (3) 1993: 221-224
1980 – 1989
- 1989
- [c1]Gilles Privat, Marc Renaudin:
Motion estimation VLSI architecture for image coding. ICCD 1989: 78-81
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-09 00:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
