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2020 – today
- 2024
[c41]Michael Hart
, John McAllister:
Quantum Circuit Cutting Minimising Loss of Qubit Entanglement. CF 2024- [c40]Michael Hart, John McAllister:
Reconstructing Cut Quantum Circuits Maximising Fidelity between Quantum States. CF 2024 - 2023
- [j25]Viraj Singh Gaur, Vishal Sharma, John McAllister:
Abusive adversarial agents and attack strategies in cyber-physical systems. CAAI Trans. Intell. Technol. 8(1): 149-165 (2023) - [j24]Timoteo García Bertoa, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, John McAllister:
Fault-Tolerant Neural Network Accelerators With Selective TMR. IEEE Des. Test 40(2): 67-74 (2023) - 2022
- [j23]Vishal Sharma, Blesson Varghese, John McAllister, Saraju P. Mohanty:
Abusive Adversaries in 5G and Beyond IoT. IEEE Consumer Electron. Mag. 11(4): 11-20 (2022) - [j22]John McAllister:
Editorial. J. Signal Process. Syst. 94(8): 771 (2022) - [c39]Jarlath Warner, Richard Gault, John McAllister:
Optimised EMG pipeline for gesture classification. EMBC 2022: 3628-3631 - 2021
- [j21]Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón:
EMG Biometric Systems Based on Different Wrist-Hand Movements. IEEE Access 9: 12256-12266 (2021) - [j20]John McAllister, Mike Polley, Roozbeh Jafari:
The Applied Signal Processing Systems Technical Committee [In the Spotlight]. IEEE Signal Process. Mag. 38(1): 137-139 (2021) - [j19]Yun Wu, John McAllister:
Configurable Quasi-Optimal Sphere Decoding for Scalable MIMO Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2675-2687 (2021) - [j18]John McAllister:
Algorithms & Architectures at the Boundary of Signal Processing & Machine Learning. J. Signal Process. Syst. 93(10): 1115 (2021) - [c38]Michael Hart, John McAllister, Leo Rogers, Charles Gillan:
An Emulation of Quantum Error-Correction on an FPGA device. FPL 2021: 104-108 - [c37]Yun Wu, John McAllister:
Energy-Efficient Adaptive Modulated Fixed-Complexity Sphere Decoder. SiPS 2021: 82-87 - 2020
- [j17]Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón:
Real-Time Embedded EMG Signal Analysis for Wrist-Hand Pose Identification. IEEE Trans. Signal Process. 68: 2713-2723 (2020) - [j16]Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty:
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92(10): 1039-1041 (2020) - [j15]Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty:
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92(10): 1043 (2020) - [c36]Yun Wu, Peng Wang, John McAllister:
Programmable Dataflow Accelerators: A 5G OFDM Modulation/Demodulation Case Study. ICASSP 2020: 1728-1732 - [c35]John McAllister, Michael Davis:
Graph Coordination for Compact Representation of Regular Dataflow Structures. SiPS 2020: 1-6
2010 – 2019
- 2019
- [c34]Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón:
EMG Wrist-hand Motion Recognition System for Real-time Embedded Platform. ICASSP 2019: 1523-1527 - [c33]Yun Wu, John McAllister:
On Modified Squared Givens Rotations for Sphere Decoder Preprocessing. ICASSP 2019: 1528-1531 - [c32]Leo Rogers, John McAllister:
Window Size Estimation for Nearest Neighbour Compliant Quantum Circuit Mapping. ISCAS 2019: 1-5 - [c31]Leo Rogers, John McAllister:
Comparison of Exponentially Decreasing Vs. Polynomially Decreasing Objective Functions for Making Quantum Circuits Nearest Neighbour Compliant. SAMOS 2019: 348-357 - 2018
- [j14]Yun Wu, John McAllister:
Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA. IEEE Trans. Parallel Distributed Syst. 29(1): 43-55 (2018) - [c30]Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón:
Emg Acquisition and Hand Pose Classification for Bionic Hands from Randomly-Placed Sensors. ICASSP 2018: 1105-1109 - 2017
- [j13]Yun Wu, John McAllister:
Bounded Selective Spanning With Extended Fast Enumeration for MIMO-OFDM Systems Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2556-2568 (2017) - [c29]Stephen Laide, John McAllister:
Multicore distributed dictionary learning: A microarray gene expression biclustering case study. ICASSP 2017: 1168-1172 - 2016
- [j12]Matthew Milford, John McAllister:
Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels. IEEE Trans. Signal Process. 64(16): 4152-4165 (2016) - [j11]Peng Wang, John McAllister:
Streaming Elements for FPGA Signal and Image Processing Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2262-2274 (2016) - [j10]John McAllister, Máire O'Neill, Maxime Pelcat:
Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies. J. Signal Process. Syst. 84(3): 293-294 (2016) - 2015
- [j9]John McAllister, David Guevorkian, Hartwig Jeschke, Mihai Sima:
Guest Editorial: Special Issue on Embedded Computer Systems: Architectures, Modeling and Simulation. Int. J. Parallel Program. 43(1): 1-2 (2015) - 2014
- [c28]Yun Wu, John McAllister:
FPGA-based Tabu search for detection in large-scale MIMO systems. SiPS 2014: 121-126 - 2013
- [j8]John McAllister, Luigi Carro, Skevos Evripidou:
Guest Editorial: Special Issue on 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI). Int. J. Parallel Program. 41(2): 161-162 (2013) - [c27]Yun Wu, John McAllister:
Bounded selective spanning with extended fast enumeration for MIMO-OFDM systems detection. EUSIPCO 2013: 1-5 - [c26]Ciara Moore, Neil Hanley, John McAllister, Máire O'Neill, Elizabeth O'Sullivan, Xiaolin Cao:
Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE. Financial Cryptography Workshops 2013: 226-237 - [c25]Peng Wang, John McAllister, Yun Wu:
Software defined FFT architecture for IEEE 802.11ac. GlobalSIP 2013: 1246-1249 - [c24]Yun Wu, John McAllister, Peng Wang:
High performance real-time Pre-Processing for Fixed-Complexity Sphere Decoder. GlobalSIP 2013: 1250-1253 - [c23]Peng Wang, John McAllister, Yun Wu:
Soft-core stream processing on FPGA: An FFT case study. ICASSP 2013: 2756-2760 - [c22]Peng Wang, John McAllister:
Soft-core stream processor for sliding window applications. SiPS 2013: 213-218 - [p2]John McAllister:
FPGA-Based DSP. Handbook of Signal Processing Systems 2013: 707-739 - 2012
- [j7]Xuezheng Chu, John McAllister:
Software-Defined Sphere Decoding for FPGA-Based MIMO Detection. IEEE Trans. Signal Process. 60(11): 6017-6026 (2012) - [c21]Matthew Milford, John McAllister:
Memory-centric VDF graph transformations for practical FPGA implementation. ESTIMedia 2012: 12-18 - [c20]Matthew Milford, John McAllister:
Valved dataflow for FPGA memory hierarchy synthesis. ICASSP 2012: 1645-1648 - [c19]John McAllister, Shuvra S. Bhattacharyya:
Preface. ICSAMOS 2012 - [c18]Matthew Milford, John McAllister:
Automatic FPGA synthesis of memory intensive C-based kernels. ICSAMOS 2012: 136-143 - 2011
- [j6]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny:
QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. IEEE Trans. Signal Process. 59(4): 1858-1867 (2011) - [j5]C. Zheng, Xuezheng Chu, John McAllister, Roger F. Woods:
Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems. IEEE Trans. Signal Process. 59(9): 4493-4499 (2011) - [c17]Xuezheng Chu, John McAllister, Roger F. Woods:
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. ARC 2011: 133-144 - [c16]Chengwei Zheng, John McAllister, Yun Wu:
A kernel interleaved scheduling method for streaming applications on soft-core vector processors. ICSAMOS 2011: 278-285 - [e1]Andreas Koch, Ram Krishnamurthy, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi:
Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Lecture Notes in Computer Science 6578, Springer 2011, ISBN 978-3-642-19474-0 [contents] - 2010
- [j4]Scott Fischaber, Roger F. Woods, John McAllister:
SoC Memory Hierarchy Derivation from Dataflow Graphs. J. Signal Process. Syst. 60(3): 345-361 (2010) - [c15]Xuezheng Chu, John McAllister:
FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case study. FPT 2010: 479-484 - [p1]John McAllister:
FPGA-based DSP. Handbook of Signal Processing Systems 2010: 363-392
2000 – 2009
- 2009
- [c14]John McAllister:
Evolutionary requirements for next-generation dataflow-based FPGA system design. EUSIPCO 2009: 2688-2692 - 2008
- [c13]Stephen McKeown, Roger F. Woods, John McAllister:
Power efficient DSP datapath configuration methodology for FPGA. FPL 2008: 515-518 - [c12]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny:
Modified givens rotations and their application to matrix inversion. ICASSP 2008: 1437-1440 - [c11]John McAllister:
Introduction to System Level Design for Heterogeneous Systems. SAMOS 2008: 146 - [c10]Scott Fischaber, John McAllister, Roger F. Woods:
Memory-Centric Hardware Synthesis from Dataflow Models. SAMOS 2008: 197-206 - [c9]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai:
Reduced-complexity MSGR-based matrix inversion. SiPS 2008: 124-128 - [c8]Stephen McKeown, Roger F. Woods, John McAllister:
Power efficient dynamic-range utilisation for DSP on FPGA. SiPS 2008: 233-238 - 2007
- [j3]John McAllister, Roger F. Woods, Scott Fischaber, E. Malins:
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. J. Syst. Archit. 53(8): 511-523 (2007) - [j2]Erdem Motuk, Roger F. Woods, Stefan Bilbao, John McAllister:
Design Methodology for Real-Time FPGA-Based Sound Synthesis. IEEE Trans. Signal Process. 55(12): 5833-5845 (2007) - [c7]Scott Fischaber, Roger F. Woods, John McAllister:
SOC Memory Hierarchy Derivation from Dataflow Graphs. SiPS 2007: 469-474 - 2006
- [j1]John McAllister, Roger F. Woods, Richard L. Walke, Darren Gerard Reilly:
Multidimensional DSP Core Synthesis for FPGA. J. VLSI Signal Process. 43(2-3): 207-221 (2006) - [c6]Scott Fischaber, John McAllister, Roger F. Woods, E. Malins:
Muir Hardware Synthesis for Multimedia Applications. ESTIMedia 2006: 101-106 - 2005
- [c5]Jasmine Lam, John McAllister, Jennifer Dudley:
Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs. FCCM 2005: 325-326 - [c4]Scott Fischaber, R. Hasson, John McAllister, Roger F. Woods:
FPGA Core Network Implementation and Optimization: A Case Study. FPT 2005: 319-320 - [c3]Darren Gerard Reilly, Roger F. Woods, John McAllister, Richard L. Walke:
Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications]. ICASSP (5) 2005: 65-68 - [c2]John McAllister, Roger F. Woods, Darren Gerard Reilly, Scott Fischaber, R. Hasson:
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. SAMOS 2005: 414-423 - 2004
- [c1]John McAllister, Roger F. Woods, Richard L. Walke:
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. SAMOS 2004: 254-263
Coauthor Index
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last updated on 2024-12-08 02:26 CET by the dblp team
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