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Jong Wook Kwak
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2020 – today
- 2024
- [j24]Kyung-Min Kim, Jong Wook Kwak:
PVS-GEN: Systematic Approach for Universal Synthetic Data Generation Involving Parameterization, Verification, and Segmentation. Sensors 24(1): 266 (2024) - 2023
- [j23]Sang-Ho Hwang, Kyung-Min Kim, Sungho Kim, Jong Wook Kwak:
Lossless Data Compression for Time-Series Sensor Data Based on Dynamic Bit Packing. Sensors 23(20): 8575 (2023) - 2022
- [j22]Kyungmin Kim, Jiung Song, Jong Wook Kwak:
PRIGM: Partial-Regression-Integrated Generic Model for Synthetic Benchmarks Robust to Sensor Characteristics. IEICE Trans. Inf. Syst. 105-D(7): 1330-1334 (2022) - 2020
- [j21]Jun-Hyeong Choi, Kyung Min Kim, Jong Wook Kwak:
WPA: Write Pattern Aware Hybrid Disk Buffer Management for Improving Lifespan of NAND Flash Memory. IEEE Trans. Consumer Electron. 66(2): 193-202 (2020)
2010 – 2019
- 2018
- [j20]Sang-Ho Hwang, Jong Wook Kwak:
RbWL: Recency-Based Static Wear Leveling for Lifetime Extension and Overhead Reduction in NAND Flash Memory Systems. IEICE Trans. Inf. Syst. 101-D(10): 2518-2522 (2018) - [j19]Sungho Kim, Sang-Ho Hwang, Jong Wook Kwak:
Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory. Microprocess. Microsystems 57: 65-75 (2018) - 2017
- [j18]Seon Hwan Kim, Ju Hee Choi, Jong Wook Kwak:
RRWL: Round Robin-Based Wear Leveling Using Block Erase Table for Flash Memory. IEICE Trans. Inf. Syst. 100-D(5): 1124-1127 (2017) - [j17]Ju Hee Choi, Jong Wook Kwak:
Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1236-1249 (2017) - 2016
- [j16]Seon Hwan Kim, Ju Hee Choi, Jong Wook Kwak:
HaWL: Hidden Cold Block-Aware Wear Leveling Using Bit-Set Threshold for NAND Flash Memory. IEICE Trans. Inf. Syst. 99-D(4): 1242-1245 (2016) - [j15]Seon Hwan Kim, Ju Hee Choi, Jong Wook Kwak:
PBGC: Proxy Block-Based Garbage Collection for Index Structures in NAND Flash Memory. IEICE Trans. Inf. Syst. 99-D(7): 1928-1932 (2016) - [j14]Sang-Ho Hwang, Ju Hee Choi, Jong Wook Kwak:
Migration Cost Sensitive Garbage Collection Technique for Non-Volatile Memory Systems. IEICE Trans. Inf. Syst. 99-D(12): 3177-3180 (2016) - 2015
- [c16]Min-Kyu Kim, Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Bypassing method for STT-RAM based inclusive last-level cache. RACS 2015: 424-429 - 2014
- [j13]Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor. IEICE Trans. Inf. Syst. 97-D(4): 972-975 (2014) - [j12]Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon:
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor. IEICE Trans. Inf. Syst. 97-D(8): 2166-2169 (2014) - [c15]Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Adaptive cache compression for non-volatile memories in embedded system. RACS 2014: 52-57 - 2013
- [j11]Young-Sik Eom, Jong Wook Kwak, Seong Tae Jhang, Chu-Shik Jhon:
Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors. IEICE Trans. Inf. Syst. 96-D(2): 370-374 (2013) - [c14]Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Data filter cache with word selection cache for low power embedded processor. RACS 2013: 422-427 - 2012
- [j10]Young-Sik Eom, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors. IEICE Trans. Inf. Syst. 95-D(6): 1676-1679 (2012) - 2010
- [j9]Jong Wook Kwak, Young Tae Jeon:
Compressed tag architecture for low-power embedded cache systems. J. Syst. Archit. 56(9): 419-428 (2010) - [j8]Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, Tae-Jin Kim, Sung-Bae Park:
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC). Microprocess. Microsystems 34(2-4): 102-116 (2010) - [c13]Jong Wook Kwak, Ju Hee Choi:
Selective Access to Filter Cache for Low-Power Embedded Systems. HICSS 2010: 1-8
2000 – 2009
- 2009
- [c12]Jong Wook Kwak, Ju-Hwan Kim:
Performance Evaluation Model of Branch Input Vectors using Neural Network. CDES 2009: 31-37 - 2008
- [j7]Jong Wook Kwak, Chu Shik Jhon:
High-performance embedded branch predictor by combining branch direction history and global branch history. IET Comput. Digit. Tech. 2(2): 142-154 (2008) - 2007
- [j6]Jong Wook Kwak, Chu Shik Jhon:
Dynamic per-branch history length adjustment to improve branch prediction accuracy. Microprocess. Microsystems 31(1): 63-76 (2007) - [j5]Jong Wook Kwak, Chu Shik Jhon:
Torus Ring: improving performance of interconnection network by modifying hierarchical ring. Parallel Comput. 33(1): 2-20 (2007) - [c11]Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park:
Performance monitor unit design for an AXI-based multi-core SoC platform. SAC 2007: 1565-1572 - 2006
- [j4]Jong Wook Kwak, Cheol Hong Kim, Sung-Hoon Shim, Chu Shik Jhon:
Advanced High-Level Cache Management by Processor Access Information. J. Inf. Sci. Eng. 22(1): 215-227 (2006) - [j3]Jong Wook Kwak, Chu Shik Jhon:
Adaptive Multi-Grain Remote Access Cache in Ring Based NUMA System. J. Inf. Sci. Eng. 22(6): 1543-1554 (2006) - [c10]Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Accuracy Enhancement by Selective Use of Branch History in Embedded Processor. International Conference on Computational Science (4) 2006: 979-986 - [c9]Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
History Length Adjustable gshare Predictor for High-Performance Embedded Processor. ICCSA (4) 2006: 631-638 - [c8]Jong Wook Kwak, Chu Shik Jhon:
Recovery Logics for Speculative Update Global and Local Branch History. ISCIS 2006: 258-266 - 2005
- [j2]Jong Wook Kwak, Hyong Jin Ban, Chu Shik Jhon:
Torus Ring: Improving Interconnection Network Performance by Modifying Hierarchical Ring. IEICE Trans. Inf. Syst. 88-D(5): 1067-1071 (2005) - [j1]Jong Wook Kwak, Ju-Hwan Kim, Chu Shik Jhon:
The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction. IEICE Trans. Inf. Syst. 88-D(7): 1754-1758 (2005) - [c7]Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon:
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. SAMOS 2005: 103-111 - [c6]Sung-Hoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon:
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic. SAMOS 2005: 162-171 - 2004
- [c5]Cheol Hong Kim, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information. EUC 2004: 1-11 - [c4]Sung-Hoon Shim, Cheol Hong Kim, Jong Wook Kwak, Chu Shik Jhon:
Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor. EUC 2004: 74-84 - [c3]Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Chu Shik Jhon:
A Novel Approach to Improve Cache Performance in Ring-Based Multiprocessors. PDPTA 2004: 519-524 - [c2]Jong Wook Kwak, Hyunbae Lee, Cheol Hong Kim, Sung-Hoon Shim, Chu Shik Jhon:
Level 1 & Victim Cache Management with Processor Reuse Information. PDPTA 2004: 694-698 - [c1]Soong Hyun Shin, Jong Wook Kwak, Chu Shik Jhon:
Ownership-Lacking Line First Policy of Remote Access Cache in NUMA System. PDPTA 2004: 1319-1323
Coauthor Index
aka: Chu-Shik Jhon
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