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2010 – 2019
- 2014
[j4]J. Rubén Titos Gil
, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25(5): 1359-1369 (2014)- [c11]Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström:
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS 2014: 615-624 - 2013
- [j3]Anurag Negi, J. Rubén Titos Gil:
SCIN-cache: Fast speculative versioning in multithreaded cores. ACM Trans. Archit. Code Optim. 9(4): 58:1-58:26 (2013) - [j2]Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal:
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10(4): 42:1-42:25 (2013) - [j1]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(11): 2192-2201 (2013) - [c10]Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris:
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC 2013: 196-205 - [c9]Madhavan Manivannan, Anurag Negi, Per Stenström:
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP 2013: 517-522 - 2012
- [c8]Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström:
Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT 2012: 181-190 - [c7]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152 - 2011
- [c6]Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204 - [c5]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82 - [c4]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62 - [c3]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707 - 2010
- [c2]Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. IFMT 2010: 5:1-5:10 - [c1]Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: A low complexity lazy versioning HTM infrastructure. ICSAMOS 2010: 231-240
Coauthor Index
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