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ORCIDSteven M. Burns
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
- affiliation (former): University of Washington, Department of Computer Science and Engineering, Seattle, WA, USA
Other persons with the same name
- Steven Burns 0001 (aka: Steve Burns 0001) — Globalfoundries, Essex Junction, VT, USA (and 1 more)
Other persons with a similar name
- Steven Burns — disambiguation page
- Steven R. Burns
- Steven W. Burns — Int. Paper Co., Jay, ME, USA
- Steven Burns 0002 — Burns Industries Inc., Nashua, NH, USA
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2020 – today
- 2023
[j17]Kishor Kunal
, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023)- [j16]Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - [c33]Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC 2023: 475-482 - 2022
- [c32]Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar:
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE 2022: 148-153 - [c31]Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166 - 2021
- [j15]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [c30]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE 2021: 1224-1229 - [c29]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD 2021: 1-9 - [c28]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [i2]Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang:
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. CoRR abs/2111.15024 (2021) - 2020
- [c27]Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c26]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c25]Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar:
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [i1]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020)
2010 – 2019
- 2019
- [c24]Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77 - [c23]Nikolay Ryzhenko, Steven M. Burns, Anton Sorokin, Mikhail Talalay:
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints. ISPD 2019: 41-47 - 2018
- [j14]Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven M. Burns, Ozcan Ozturk:
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 420-430 (2018) - [c22]Michael Barrow, Steven M. Burns, Ryan Kastner:
A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation. FPL 2018: 335-342 - 2017
- [j13]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk:
Graph Analytics Accelerators for Cognitive Systems. IEEE Micro 37(1): 42-51 (2017) - 2016
- [c21]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk:
Energy Efficient Architecture for Graph Analytics Accelerators. ISCA 2016: 166-177 - 2015
- [j12]Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 381-394 (2015) - [c20]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. ICCAD 2015: 676-681 - [c19]Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Hardware Accelerator Design for Data Centers. ICCAD 2015: 770-775 - 2013
- [c18]Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
Trace alignment algorithms for offline workload analysis of heterogeneous architectures. ICCAD 2013: 654-661 - [c17]Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo:
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. ISPD 2013: 168-170 - 2012
- [j11]Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu:
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1558-1571 (2012) - [c16]Nikolai Ryzhenko, Steven M. Burns:
Standard cell routing via boolean satisfiability. DAC 2012: 603-612 - [c15]Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo:
The ISPD-2012 discrete cell sizing contest and benchmark suite. ISPD 2012: 161-164 - 2011
- [c14]Nikolai Ryzhenko, Steven M. Burns:
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. DAC 2011: 83-88 - [c13]Andrey Ayupov, Steven M. Burns:
A trace compression algorithm targeting power estimation of long benchmarks. ICCAD 2011: 702-707 - [c12]Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu:
Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD 2011: 724-731
2000 – 2009
- 2007
- [c11]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - 2002
- [j10]Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev:
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 109-130 (2002) - [c10]Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491
1990 – 1999
- 1999
- [c9]Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken:
CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121 - [c8]Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens:
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD 1999: 324-331 - 1998
- [j9]William Chan, Richard J. Anderson, Paul Beame, Steve Burns, Francesmary Modugno, David Notkin, Jon Damon Reese:
Model Checking Large Software Specifications. IEEE Trans. Software Eng. 24(7): 498-520 (1998) - 1997
- [j8]Henrik Hulgaard, Steven M. Burns:
Bounded Delay Timing Analysis of a Class of CSP Programs. Formal Methods Syst. Des. 11(3): 265-294 (1997) - 1996
- [c7]Steven M. Burns:
General conditions for the decomposition of state holding elements. ASYNC 1996: 48-57 - [c6]Richard J. Anderson, Paul Beame, Steve Burns, William Chan, Francesmary Modugno, David Notkin, Jon Damon Reese:
Model Checking Large Software Specifications. SIGSOFT FSE 1996: 156-166 - 1995
- [j7]Henrik Hulgaard, Steven M. Burns, Gaetano Borriello:
Testing asynchronous circuits: A survey. Integr. 19(3): 111-131 (1995) - [j6]Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello:
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE Trans. Computers 44(11): 1306-1317 (1995) - [j5]Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns:
Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 473-482 (1995) - [j4]Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns:
The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 491-501 (1995) - [c5]Henrik Hulgaard, Steven M. Burns:
Efficient Timing Analysis of a Class of Petri Nets. CAV 1995: 423-436 - 1994
- [j3]Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling:
An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. 11(3): 60-69 (1994) - [c4]Henrik Hulgaard, Steven M. Burns:
Bounded delay timing analysis of a class of CSP programs with choice. ASYNC 1994: 2-11 - 1993
- [c3]Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello:
Practical applications of an efficient time separation of events algorithm. ICCAD 1993: 146-151 - [c2]Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello:
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. ICCD 1993: 166-173 - 1992
- [c1]Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling:
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL 1992: 44-51 - 1991
- [b1]Steven Morgan Burns:
Performance analysis and optimization of asynchronous circuits. California Institute of Technology, USA, 1991
1980 – 1989
- 1989
- [j2]Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus:
The first asynchronous microprocessor: the test results. SIGARCH Comput. Archit. News 17(4): 95-98 (1989) - [j1]Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus:
The design of an asynchronous microprocessor. SIGARCH Comput. Archit. News 17(4): 99-110 (1989)
Coauthor Index
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