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ORCIDPatrick Girard 0001
Person information
- affiliation: University of Montpellier, LRIMM
Other persons with the same name
- Patrick Girard — disambiguation page
- Patrick Girard 0002 — University of Poitiers, LIAS/ISAE-ENSMA
- Patrick Girard 0003 — NRC Canada, Industrial Materials Institute
- Patrick Girard 0004
![[0000-0002-7722-0023]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7722-0023")
— University of Auckland, Department of Philosophy, New Zealand - Patrick Girard 0005 — INSA Lyon, CREATIS
Other persons with a similar name
- Patrick R. Girard — University of Lyon, CREATIS
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2020 – today
- 2024
[j80]Aibin Yan, Zhixing Li, Zhongyu Gao, Jing Zhang, Zhengfeng Huang, Tianming Ni, Jie Cui, Xiaolei Wang, Patrick Girard, Xiaoqing Wen:
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2205-2214 (2024)- [j79]Aibin Yan, Yu Chen, Zhongyu Gao, Tianming Ni, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2299-2303 (2024) - [j78]Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 116-127 (2024) - [c234]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE 2024: 1-6 - [c233]Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel:
A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology. DFT 2024: 1-4 - [c232]Aibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen:
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2024: 19-24 - [c231]Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel:
A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS 2024: 1-6 - [c230]Aibin Yan, Zhuoyuan Lin, Guangzhu Liu, Qingyang Zhang, Zhengfeng Huang, Jie Cui, Xiaoqing Wen, Patrick Girard:
Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. ISCAS 2024: 1-5 - [c229]Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel:
A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. ITC 2024: 270-279 - 2023
- [j77]Aibin Yan, Yuting He, Xiaoxiao Niu, Jie Cui, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. IEEE Des. Test 40(4): 34-41 (2023) - [j76]Aibin Yan, Jing Xiang, Yang Chang, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. Microelectron. J. 139: 105908 (2023) - [j75]Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. 59(3): 2885-2897 (2023) - [j74]Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2069-2073 (2023) - [j73]Aibin Yan, Runqi Liu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang:
Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2256-2260 (2023) - [j72]Aibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang:
Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. IEEE Trans. Emerg. Top. Comput. 11(4): 1070-1081 (2023) - [c228]Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. DATE 2023: 1-2 - [c227]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS 2023: 1-4 - [c226]Xhesila Xhafa, Patrick Girard, Arnaud Virazel:
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS 2023: 1-2 - [c225]Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel:
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS 2023: 1-4 - [c224]Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2023: 167-171 - [c223]Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of Low-Cost Approximate CMOS Full Adders. ISCAS 2023: 1-5 - [c222]J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel:
Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. ITC 2023: 310-319 - [c221]Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. ITC-Asia 2023: 1-6 - [c220]Aibin Yan, Fan Xia, Tianming Ni, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Low Overhead and Double-Node-Upset Self-Recoverable Latch. ITC-Asia 2023: 1-5 - [c219]Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. ITC-Asia 2023: 1-6 - 2022
- [j71]Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard:
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. ACM J. Emerg. Technol. Comput. Syst. 18(4): 71:1-71:20 (2022) - [j70]Aibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard, Xiaoqing Wen:
Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. IEEE Trans. Aerosp. Electron. Syst. 58(1): 517-529 (2022) - [j69]Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. IEEE Trans. Emerg. Top. Comput. 10(1): 404-413 (2022) - [c218]Aibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. ATS 2022: 1-6 - [c217]Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard:
SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. DATE 2022: 1257-1262 - [c216]Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel:
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS 2022: 1-2 - [c215]J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel:
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS 2022: 1-2 - [c214]Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. ACM Great Lakes Symposium on VLSI 2022: 255-260 - [c213]Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2022: 261-266 - [c212]Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2022: 333-338 - [c211]P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel:
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. ITC 2022: 484-488 - [c210]Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard:
Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia 2022: 73-78 - [c209]Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. VTS 2022: 1-6 - [p1]Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test and Reliability of Approximate Hardware. Approximate Computing 2022: 233-266 - 2021
- [j68]Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. J. Electron. Test. 37(4): 489-502 (2021) - [j67]Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectron. J. 111: 105034 (2021) - [j66]Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori:
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109(2): 149-169 (2021) - [j65]Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza:
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1122-1131 (2021) - [j64]Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng:
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1325-1334 (2021) - [c208]P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel:
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE 2021: 1580-1585 - [c207]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel:
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS 2021: 1-4 - [c206]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c205]Syed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard, Michael Waltl:
Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata. ETS 2021: 1-2 - [c204]Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. ACM Great Lakes Symposium on VLSI 2021: 301-306 - [c203]Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard:
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI 2021: 307-312 - [c202]Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel:
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS 2021: 1-4 - [c201]Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard:
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS 2021: 1-7 - [c200]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED 2021: 48-53 - [c199]J. Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel:
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC 2021: 1-9 - 2020
- [j63]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman:
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36(1): 33-46 (2020) - [j62]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108(12): 2178-2194 (2020) - [j61]Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56(4): 2666-2676 (2020) - [j60]Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56(5): 3931-3940 (2020) - [j59]Aibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. IEEE Trans. Computers 69(6): 789-799 (2020) - [j58]Aibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard, Xiaoqing Wen:
Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 879-890 (2020) - [j57]Aibin Yan, Yan Chen, Yuanjie Hu, Jun Zhou, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. IEEE Trans. Circuits Syst. 67-I(12): 4684-4695 (2020) - [c198]Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard:
A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. ATS 2020: 1-5 - [c197]Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. DAC 2020: 1-6 - [c196]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Maximizing Yield for Approximate Integrated Circuits. DATE 2020: 810-815 - [c195]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [c194]Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard:
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS 2020: 1-6 - [c193]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS 2020: 1-2 - [c192]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel:
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - [c191]Panagiota Papavramidou, Michael Nicolaidis, Patrick Girard:
An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM. IOLTS 2020: 1-6 - [c190]Ambika Prasad Shah, Patrick Girard:
Impact of Aging on Soft Error Susceptibility in CMOS Circuits. IOLTS 2020: 1-4 - [c189]Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza:
A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS 2020: 1-6 - [c188]Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen:
Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. ISCAS 2020: 1-5 - [c187]Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng:
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ISQED 2020: 408-414 - [c186]Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar:
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC 2020: 1-10 - [c185]Zhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. ITC-Asia 2020: 35-40
2010 – 2019
- 2019
- [j56]Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. IEEE Access 7: 176188-176196 (2019) - [c184]Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. ATS 2019: 43-48 - [c183]Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard:
Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. ATS 2019: 55-60 - [c182]Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar:
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS 2019: 21-26 - [c181]Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard:
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS 2019: 1-4 - 2018
- [j55]Patrick Girard:
A Special Section on Low Power Electronics: A Compilation of Emerging Ideas and Efficient Solutions. J. Low Power Electron. 14(2): 185 (2018) - [j54]Patrick Girard:
A Special Section on Industrial Experiences in Low Power Electronics. J. Low Power Electron. 14(3): 373 (2018) - [j53]Patrick Girard:
A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics. J. Low Power Electron. 14(4): 459 (2018) - [j52]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray:
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6(2): 278-287 (2018) - [c180]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS 2018: 85-90 - [c179]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT 2018: 1-6 - [c178]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman:
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS 2018: 1-6 - [c177]Patrick Girard:
Power-aware testing in the Era of IoT. ISQED 2018: 17-20 - [c176]Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard:
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC 2018: 1-8 - [c175]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Testing approximate digital circuits: Challenges and opportunities. LATS 2018: 1-6 - 2017
- [j51]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - [j50]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j49]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26(8): 1740007:1-1740007:18 (2017) - [j48]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - [j47]Patrick Girard:
A Special Section on New and Future Trends in Low Power Electronics. J. Low Power Electron. 13(3): 279 (2017) - [c174]Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - [c173]G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi:
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS 2017: 1-6 - [c172]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards digital circuit approximation by exploiting fault simulation. EWDTS 2017: 1-7 - [c171]Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi:
Approximate computing: Design & test for integrated circuits. LATS 2017: 1 - 2016
- [j46]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - [j45]Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard:
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. 32(6): 721-733 (2016) - [j44]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot:
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25(3): 1640013:1-1640013:18 (2016) - [c170]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective approach for functional test programs compaction. DDECS 2016: 119-124 - [c169]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c168]Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel:
Auto-adaptive ultra-low power IC. DTIS 2016: 1-6 - [c167]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2 - [c166]Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test of low power circuits: Issues and industrial practices. ICECS 2016: 524-527 - [c165]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan:
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED 2016: 185-191 - [c164]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI 2016: 731-736 - [c163]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - 2015
- [c162]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280 - [c161]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot:
Design-for-Diagnosis Architecture for Power Switches. DDECS 2015: 43-48 - [c160]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6 - [c159]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Scan-chain intra-cell defects grading. DTIS 2015: 1-6 - [c158]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard:
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c157]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20 - [c156]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94 - [c155]Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c154]Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - 2014
- [j43]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j42]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [j41]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine:
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30(5): 611-627 (2014) - [j40]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. 97-D(10): 2706-2718 (2014) - [j39]Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [j38]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay:
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2326-2335 (2014) - [c153]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c152]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray:
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS 2014: 312-317 - [c151]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Timing-aware ATPG for critical paths with multiple TSVs. DDECS 2014: 116-121 - [c150]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c149]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
Test and diagnosis of power switches. DDECS 2014: 213-218 - [c148]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri:
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - [c147]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi:
An intra-cell defect grading tool. DDECS 2014: 298-301 - [c146]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - [c145]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - [c144]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi:
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW 2014: 69-72 - [c143]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS 2014: 1-6 - 2013
- [j37]Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard:
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9(2): 253-263 (2013) - [j36]Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [j35]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 958-970 (2013) - [c142]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - [c141]Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - [c140]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 - [c139]Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c138]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS 2013: 39-44 - [c137]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c136]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS 2013: 1-6 - [c135]Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c134]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray:
Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467 - [c133]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - [c132]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC 2013: 1-10 - [c131]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné:
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c130]Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS 2013: 1-4 - [c129]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS 2013: 1-6 - 2012
- [j34]Junxia Ma, Mohammad Tehranipoor, Patrick Girard:
A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. J. Electron. Test. 28(2): 201-214 (2012) - [j33]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. J. Electron. Test. 28(2): 215-228 (2012) - [j32]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28(3): 317-329 (2012) - [j31]Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen:
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electron. 8(2): 248-258 (2012) - [c128]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130 - [c127]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot:
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium 2012: 161-166 - [c126]Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka:
Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium 2012: 167-172 - [c125]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel:
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium 2012: 221-226 - [c124]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 - [c123]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS 2012: 1 - [c122]Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Through-Silicon-Via resistive-open defect analysis. ETS 2012: 1 - [c121]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Defect analysis in power mode control logic of low-power SRAMs. ETS 2012: 1 - [c120]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné:
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122 - [c119]Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On pinpoint capture power management in at-speed scan test generation. ITC 2012: 1-10 - [c118]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10 - [c117]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich:
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 - [c116]Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Advanced test methods for SRAMs. VTS 2012: 300-301 - 2011
- [c115]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c114]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c113]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 - [c112]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen:
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 - [c111]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 - [c110]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 - [c109]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 - [c108]Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch:
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232 - [c107]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 - [c106]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda:
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158 - [c105]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 - [c104]Luigi Dilillo, Paolo Rech, Jean-Marc Gallière, Patrick Girard, Frederic Wrobel, Frédéric Saigné:
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW 2011: 1-6 - [c103]Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171 - 2010
- [j30]Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. 93-D(1): 2-9 (2010) - [j29]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [j28]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) - [c102]Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo:
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 - [c101]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 - [c100]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 - [c99]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c98]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169 - [c97]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 - [c96]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. ETS 2010: 81-86 - [c95]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS 2010: 132-137 - [c94]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Setting test conditions for improving SRAM reliability. ETS 2010: 257 - [c93]Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard:
Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. ACM Great Lakes Symposium on VLSI 2010: 127-130 - [c92]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805 - [c91]Jean-Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo:
A roaming memory test bench for detecting particle induced SEUs. ITC 2010: 810 - [c90]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c89]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80
2000 – 2009
- 2009
- [j27]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. 25(2-3): 127-144 (2009) - [j26]Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3(6): 581-592 (2009) - [j25]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1556-1559 (2009) - [c88]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 - [c87]Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348 - [c86]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55 - [c85]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 - [c84]Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 - [c83]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard:
NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 - 2008
- [j24]Nicola Nicolici, Patrick Girard:
Guest Editorial. J. Electron. Test. 24(4): 325-326 (2008) - [j23]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24(4): 353-364 (2008) - [c82]Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS 2008: 397-402 - [c81]Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 - [c80]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485 - [c79]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325 - [c78]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 - [c77]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 - [c76]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 - [c75]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 - [c74]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 - [c73]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94 - 2007
- [j22]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. 23(5): 435-444 (2007) - [c72]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Fast Bridging Fault Diagnosis using Logic Information. ATS 2007: 33-38 - [c71]Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel:
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS 2007: 507-510 - [c70]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533 - [c69]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 - [c68]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis. ETS 2007: 13-20 - [c67]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS 2007: 77-84 - [c66]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS 2007: 97-104 - [c65]Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga:
A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10 - [c64]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 - [c63]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52 - [c62]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368 - 2006
- [j21]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22(1): 89-99 (2006) - [j20]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. 22(2): 161-172 (2006) - [j19]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. 22(3): 287-296 (2006) - [j18]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
Reducing Power Dissipation in SRAM during Test. J. Low Power Electron. 2(2): 271-280 (2006) - [c61]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault:
Power-Aware Test Data Compression for Embedded IP Cores. ATS 2006: 5-10 - [c60]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
Minimizing test power in SRAM through reduction of pre-charge activity. DATE 2006: 1159-1164 - [c59]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 - [c58]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 - [c57]Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113 - 2005
- [j17]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. 21(1): 43-55 (2005) - [j16]Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. 21(2): 169-179 (2005) - [j15]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. 21(5): 551-561 (2005) - [j14]Patrick Girard:
Welcome to the Journal of Low Power Electronics. J. Low Power Electron. 1(1): 1-2 (2005) - [j13]Patrick Girard, Yannick Bonhomme:
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electron. 1(1): 85-95 (2005) - [c56]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862 - [c55]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS 2005: 116-121 - [c54]Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549 - [c53]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281 - [c52]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188 - 2004
- [j12]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20(6): 647-660 (2004) - [c51]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271 - [c50]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 - [c49]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88 - [c48]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 - [c47]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS 2004: 52-57 - [c46]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS 2004: 140-145 - [c45]Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard:
An efficient scan tree design for test time reduction. ETS 2004: 174-179 - [c44]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192 - [c43]Mickaël Baron, Patrick Girard:
SUIDT: safe user interface design tool. IUI 2004: 350-351 - [c42]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138 - 2003
- [j11]Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electron. Test. 19(3): 223-231 (2003) - [c41]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri:
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255 - [c40]Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Defect-oriented dynamic fault models for embedded-SRAMs. ETW 2003: 23-28 - [c39]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW 2003: 147-152 - [c38]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128 - [c37]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 - 2002
- [j10]Patrick Girard:
Survey of Low-Power Testing of VLSI Circuits. IEEE Des. Test Comput. 19(3): 82-92 (2002) - [j9]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19(5): 44-52 (2002) - [j8]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18(2): 145-157 (2002) - [c36]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449 - [c35]Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803 - [c34]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On Using Efficient Test Sequences for BIST. VTS 2002: 145-152 - 2001
- [j7]Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. 17(3-4): 233-241 (2001) - [c33]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 - [c32]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On hardware generation of random single input change test sequences. ETW 2001: 117-123 - [c31]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 - [c30]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89 - [c29]Guillaume Patry, Patrick Girard:
End-User Programming in a Structured Dialogue Environment: the GIPSE Project. HCC 2001: 212- - [c28]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 - 2000
- [j6]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16(3): 193-202 (2000) - [c27]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464 - [c26]Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay fault testing: choosing between random SIC and random MIC test sequences. ETW 2000: 9-14 - [c25]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126 - [c24]Patrick Girard:
Low Power Testing of VLSI Circuits: Problems and Solutions. ISQED 2000: 173-180 - [c23]Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661 - [c22]Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault:
Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS 2000: 359-368
1990 – 1999
- 1999
- [j5]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. 14(1-2): 95-102 (1999) - [c21]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 - [c20]Guillaume Patry, Patrick Girard:
GIPSE, A Model-Based System for CAD Software. CADUI 1999: 61-72 - [c19]Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
On calculating efficient LFSR seeds for built-in self test. ETW 1999: 7-14 - [c18]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. ETW 1999: 165-170 - [c17]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24- - [c16]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 - [c15]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412 - 1998
- [c14]Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium 1998: 418-423 - [c13]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439 - 1997
- [j4]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac:
A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. 24(1): 37-52 (1997) - [c12]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac:
A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286 - [c11]Christophe Fagot, Patrick Girard, Christian Landrault:
On Using Machine Learning for Logic BIST. ITC 1997: 338-346 - [c10]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch:
An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100 - 1996
- [c9]P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC 1996: 79-87 - [c8]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293 - [c7]S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A new test pattern generation method for delay fault testing. VTS 1996: 296-301 - 1995
- [j3]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. 6(3): 277-294 (1995) - [j2]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
Delay fault diagnosis in sequential circuits based on path tracing. Integr. 19(3): 199-218 (1995) - [c6]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC 1995: 526-533 - [c5]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386 - 1994
- [c4]D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523 - 1993
- [c3]D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713 - 1992
- [j1]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. 9(4): 27-32 (1992) - [c2]Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360 - [c1]Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A New Reliable Method for Delay-Fault Diagnosis. VLSI Design 1992: 12-16
Coauthor Index
[p1] [c206] [c200] [j62] [c196] [c195] [c193] [c186] [c182] [j52] [c180] [c179] [c176] [c175] [j51] [j50] [j49] [j48] [c174] [c173] [c172] [c171] [j46] [j44] [c170] [c169] [c168] [c167] [c166] [c165] [c164] [c163] [c162] [c161] [c160] [c159] [c158] [c157] [c156] [c155] [c154] [j43] [j42] [j41] [j39] [j38] [c153] [c152] [c151] [c150] [c149] [c148] [c147] [c146] [c145] [c144] [c143] [j37] [j36] [j35] [c141] [c140] [c139] [c138] [c137] [c136] [c135] [c134] [c133] [c132] [c131] [c130] [c129] [j33] [j32] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [c107] [c106] [c105] [j29] [j28] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c92] [c90] [c89] [j26] [c88] [c86] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c72] [c69] [c68]
[j44] [c165] [c162] [c161] [c160] [c159] [c158] [c154] [j43] [j42] [j41] [j39] [j38] [c153] [c152] [c151] [c150] [c149] [c148] [c147] [c146] [c145] [c144] [c143] [j37] [j36] [j35] [c141] [c140] [c139] [c138] [c137] [c136] [c135] [c134] [c132] [c131] [c130] [c129] [j33] [j32] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c107] [c106] [c105] [c104] [j29] [c102] [c101] [c100] [c99] [c97] [c96] [c95] [c94] [c92] [c91] [c90] [c89] [c88] [c87] [c85] [c83] [c75] [j22] [j19] [j18] [c60] [c59] [j16] [j15] [c56] [c55] [c52] [c51] [c46] [c42] [c41]
[j27] [j26] [j23] [c78] [c77] [c76] [c74] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c63] [c62] [j21] [c61] [c58] [c57] [c54] [c53] [j12] [c50] [c48] [j11] [c37] [j9] [j8] [c36] [c35] [c34] [j7] [c33] [c32] [c31] [c30] [c28] [j6] [c27] [c26] [c25] [c23] [c22] [j5] [c21] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j4] [c12] [c11] [c10] [c9] [c8] [c7] [j3] [j2] [c6] [c5] [c4] [c3] [j1] [c2] [c1]
[c178] [j46] [c154] [j43] [j42] [c150] [c145] [c139] [c135] [c131] [c130] [j33] [j32] [c116] [c114] [c113] [c111] [c110] [c109] [c108] [c107] [c106] [c105] [j29] [j28] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c92] [c90] [c89] [j27] [j26] [j25] [c88] [c87] [c86] [c85] [c84] [c83] [j23] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [j22] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c63] [c62] [j21] [j20] [j19] [c61] [c59] [c58] [c57] [j17] [j16] [j15] [c56] [c55] [c54] [c53] [c52] [j12] [c51] [c50] [c49] [c48] [c47] [c46] [c44] [c42] [c41] [c40] [c39] [c38] [c37] [j9] [j8] [c36] [c35] [c34] [j7] [c33] [c32] [c31] [c30] [c28] [j6] [c27] [c26] [c25] [c23] [j5] [c21] [c18] [c17] [c16] [c15] [c13] [j4] [c12] [c10] [c9] [c8] [c7] [j3] [j2] [c6] [c5] [c4] [c3] [j1] [c2] [c1]
Mark M. Tehranipoor
aka: Mohammad Tehranipoor
aka: Mohammad Tehranipoor
Aida Todri
aka: Aida Todri-Sanial
aka: Aida Todri-Sanial
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