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ORCIDHu He 0001
Person information
- affiliation: Tsinghua University, School of Integrated Circuits, Beijing Innovation Center for Future Chips (ICFC), China
- affiliation (PhD 2004): Tsinghua University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Hu He — disambiguation page
- Hu He 0002 — Institute of Ethnology & Anthropology, Beijing, China (and 1 more)
Other persons with a similar name
- Cheng-hu He
- Hai-he Hu
- He Hu 0001
![[0000-0002-0849-5795]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-0849-5795")
— Renmin University of China, Beijing, China - Hexuan Hu 0001 (aka: He-xuan Hu 0001, He-Xuan Hu 0001) — Hohai University, College of Computer and Information, Key Laboratory of Water Big Data Technology of Ministry of Water Resources, China (and 2 more)
- He Hu 0002 — Tsinghua University, Institute of Microelectronics, Beijing, China
- He Hu 0003 — Dalian Maritime University, School of Science, China
- He Hu 0004 — Xi'an Jiaotong University, School of Mathematics and Statistics, China
- He Hu 0005 — Texas A&M University, Department of Electrical and Computer Engineering, College Station, TX, USA
- He Hu 0006 — Xi'an University of Science and Technology, School of Computing, China
- He Hu 0007 — Beijing Jiaotong University, School of Transportation, China
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2020 – today
- 2024
[c12]Jingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He:
HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors. ACM Great Lakes Symposium on VLSI 2024: 338-342- 2023
- [j20]Ruihua Yu, Wenqiang Zhang, Bin Gao, Yiwen Geng, Peng Yao, Yuyi Liu, Qingtian Zhang, Jianshi Tang, Dong Wu, Hu He, Ning Deng, He Qian, Huaqiang Wu:
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system. Sci. China Inf. Sci. 66(12) (2023) - [j19]Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu:
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5339-5351 (2023) - [j18]Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Jian Yu, Dabin Wu, Junren Chen, Qingtian Zhang, Xing Mou, He Qian, Huaqiang Wu:
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2734-2738 (2023) - [c11]Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Qingtian Zhang, He Qian, Huaqiang Wu:
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing. ICTA 2023: 134-135 - 2021
- [j17]Hu He, Qilin Wang, Xu Yang, Yunlin Lei, Jia Cai, Ning Deng:
A memory neural system built based on spiking neural network. Neurocomputing 442: 146-160 (2021) - [c10]Yanhai Jiang, Bin Gao, Jianshi Tang, Dabin Wu, Hu He, He Qian, Huaqiang Wu:
HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU. ICTA 2021: 35-36 - 2020
- [c9]Liya Dong, Qilin Wang, Hu He:
The Algorithm of Spiking Neural Network And Application in Poker Games. ICMSSP 2020: 60-63
2010 – 2019
- 2019
- [j16]Xu Yang, Guo Liu, Songgaojun Deng, Zichao Wei, Hu He, Yingjie Shang, Ning Deng:
Exploration of a mechanism to form bionic, self-growing and self-organizing neural network. Artif. Intell. Rev. 52(1): 585-605 (2019) - [j15]Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He, Xu Yang:
Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods. J. Circuits Syst. Comput. 28(2): 1950020:1-1950020:20 (2019) - [j14]Xu Yang, Yumin Hou, Hu He:
A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications. Sensors 19(1): 140 (2019) - [j13]Xu Yang, Yumin Hou, Junping Ma, Hu He:
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things. Sensors 19(3): 556 (2019) - [j12]Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu:
On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1820-1830 (2019) - [c8]Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian:
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. DAC 2019: 140 - 2018
- [c7]Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu:
R2D2: Runtime reassurance and detection of A2 Trojan. HOST 2018: 195-200 - 2017
- [j11]Hu He, Xu Yang, Yanjun Zhang:
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage. Comput. J. 60(9): 1338-1352 (2017) - 2016
- [j10]Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu:
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. VLSI Design 2016: 8787919:1-8787919:12 (2016) - 2014
- [j9]Xu Yang, Deyuan Guo, Hu He, Haijing Tang, Yanjun Zhang:
An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems. Comput. J. 57(11): 1756-1764 (2014) - [j8]Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He:
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2629-2634 (2014) - 2013
- [j7]Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He:
Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. IET Wirel. Sens. Syst. 3(2) (2013) - 2012
- [j6]Xu Yang, Hu He:
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems. Sensors 12(4): 4466-4478 (2012) - 2011
- [j5]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. J. Electron. Test. 27(5): 647-655 (2011) - [j4]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. J. Electron. Test. 27(5): 679 (2011) - [c6]Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan:
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). FPGA 2011: 281
2000 – 2009
- 2009
- [j3]Yang Xu, Hu He, Yihe Sun:
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. J. Low Power Electron. 5(2): 123-134 (2009) - [c5]Zheng Shen, Hu He, Yihe Sun:
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. DSD 2009: 505-512 - 2008
- [c4]Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei:
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. DELTA 2008: 20-25 - 2007
- [j2]Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun:
Heuristic on a Novel Power Management System Cooperating with Compiler. J. Low Power Electron. 3(1): 22-27 (2007) - [j1]Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun:
A Video Specific Instruction Set Architecture for ASIP design. VLSI Design 2007: 58431:1-58431:7 (2007) - [c3]Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng:
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. ASAP 2007: 371-376 - 2006
- [c2]Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun:
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. IIH-MSP 2006: 587-592 - 2005
- [c1]Yanjun Zhang, Hu He, Yihe Sun:
A new register file access architecture for software pipelining in VLIW processors. ASP-DAC 2005: 627-630
Coauthor Index
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