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2020 – today
- 2025
[j21]Maël Tourres, Cyrille Chavet
, Bertrand Le Gal, Philippe Coussy:
Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors. IEEE Access 13: 6964-6976 (2025)- 2024
- [j20]Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs. IEEE Trans. Parallel Distributed Syst. 35(7): 1293-1306 (2024) - [c67]Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications. DASIP 2024: 83-95 - [c66]Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy:
SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs. DSD 2024: 242-249 - 2023
- [j19]Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy:
An Efficient and Flexible Stochastic CGRA Mapping Approach. ACM Trans. Embed. Comput. Syst. 22(1): 8:1-8:24 (2023) - 2022
- [j18]Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Energy Efficient Hardware Loop Based Optimization for CGRAs. J. Signal Process. Syst. 94(9): 895-912 (2022) - [j17]Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy:
Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions. J. Signal Process. Syst. 94(10): 945-960 (2022) - [p1]Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat:
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud. Behavioral Synthesis for Hardware Security 2022: 71-93 - 2021
- [j16]Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Floating Point CGRA based Ultra-Low Power DSP Accelerator. J. Signal Process. Syst. 93(10): 1159-1171 (2021) - [c65]Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy:
Extended RISC-V hardware architecture for future digital communication systems. 5GWF 2021: 224-229 - [c64]Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Hardware Based Loop Optimization for CGRA Architectures. ARC 2021: 65-80 - [c63]Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat:
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. DATE 2021: 52-55 - [c62]Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy:
Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators. SiPS 2021: 123-128 - 2020
- [c61]Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi:
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE 2020: 1067-1072 - [c60]Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy:
Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. ICASSP 2020: 1563-1567 - [c59]Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy:
Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. ISCAS 2020: 1-4 - [c58]Nermine Ali, Jean-Marc Philippe, Benoît Tain, Thomas Peyret, Philippe Coussy:
Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems. SiPS 2020: 1-6
2010 – 2019
- 2019
- [j15]Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini:
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1095-1108 (2019) - [j14]Hugues Wouafo, Cyrille Chavet, Philippe Coussy:
Clone-Based Encoded Neural Networks to Design Efficient Associative Memories. IEEE Trans. Neural Networks Learn. Syst. 30(10): 3186-3199 (2019) - [c57]Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs. DATE 2019: 336-341 - [c56]Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat:
Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment. DATE 2019: 1118-1123 - [c55]Cyrille Chavet, Fabrice Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy:
Solving Memory Access Conflicts in LTE-4G Standard. ICASSP 2019: 1518-1522 - 2018
- [c54]Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi:
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. ISCAS 2018: 1-5 - 2017
- [j13]Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec:
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 384-397 (2017) - [c53]Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini:
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. ASP-DAC 2017: 127-132 - [c52]Satyajit Das, Davide Rossi, Kevin J. M. Martin, Philippe Coussy, Luca Benini:
A 142MOPS/mW integrated programmable array accelerator for smart visual processing. ISCAS 2017: 1-4 - [c51]Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo:
Efficient scalable hardware architecture for highly performant encoded neural networks. SiPS 2017: 1-6 - 2016
- [c50]Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy:
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. DASIP 2016: 51-58 - [c49]Awais Sani, Philippe Coussy, Cyrille Chavet:
A dynamically reconfigurable ECC decoder architecture. DATE 2016: 1437-1440 - [c48]Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy:
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI 2016: 655-660 - 2015
- [j12]Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Laura Conde-Canencia:
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. ACM J. Emerg. Technol. Comput. Syst. 11(4): 35:1-35:23 (2015) - [j11]Jeffrey L. Krichmar, Philippe Coussy, Nikil D. Dutt:
Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models. ACM J. Emerg. Technol. Comput. Syst. 11(4): 36:1-36:18 (2015) - [c47]Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani:
In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE 2015: 896-899 - [c46]Robin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross:
Restricted Clustered Neural Network for Storing Real Data. ACM Great Lakes Symposium on VLSI 2015: 205-210 - [c45]Hugues Wouafo, Cyrille Chavet, Philippe Coussy:
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. ISCAS 2015: 577-580 - [c44]Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross:
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. ISCAS 2015: 2501-2504 - 2014
- [c43]Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy:
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP 2014: 169-172 - [c42]Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini:
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters. DATE 2014: 1-4 - [c41]Paolo Burgio, Andrea Marongiu, Philippe Coussy, Luca Benini:
A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory. EUC 2014: 130-137 - [c40]Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy:
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. ACM Great Lakes Symposium on VLSI 2014: 193-198 - [c39]Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy:
An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI 2014: 229-230 - [c38]Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec:
A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator. ACM Great Lakes Symposium on VLSI 2014: 273-278 - [c37]Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy:
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP 2014: 5036-5040 - [c36]Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet:
A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. ICECS 2014: 742-745 - [c35]Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec:
A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators. ISCAS 2014: 165-168 - 2013
- [j10]Vianney Lapotre, Philippe Coussy, Cyrille Chavet:
Introduction de la prédiction de branchement dans la synthèse de haut niveau. Tech. Sci. Informatiques 32(2): 281-301 (2013) - [j9]Awais Hussain Sani, Philippe Coussy, Cyrille Chavet:
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Trans. Signal Process. 61(16): 4127-4140 (2013) - [c34]Paolo Burgio, Andrea Marongiu, Robin Danilo, Philippe Coussy, Luca Benini:
Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters. DASIP 2013: 22-29 - [c33]Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo:
Dynamic branch prediction for high-level synthesis. FPL 2013: 1-6 - [c32]Aroua Briki, Cyrille Chavet, Philippe Coussy:
A memory mapping approach for network and controller optimization in parallel interleaver architectures. ACM Great Lakes Symposium on VLSI 2013: 321-322 - [c31]Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet:
On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP 2013: 2751-2755 - [c30]Aroua Briki, Cyrille Chavet, Philippe Coussy:
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller. SiPS 2013: 201-206 - 2012
- [j8]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang:
ESL Design Methodology. J. Electr. Comput. Eng. 2012: 358281:1-358281:2 (2012) - [c29]Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini:
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. DSD 2012: 751-758 - [c28]Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin:
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI 2012: 153-158 - [c27]Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo:
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS 2012: 288-293 - 2011
- [c26]Philippe Coussy, Dominique Heller, Cyrille Chavet:
High-Level Synthesis: On the path to ESL design. ASICON 2011: 1098-1101 - [c25]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP 2011: 1613-1616 - [c24]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS 2011: 1720-1723 - 2010
- [j7]Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet:
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1736-1749 (2010) - [c23]Philippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith:
An introduction to the SystemC synthesis subset standard. CODES+ISSS 2010: 183-184 - [c22]Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin:
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL 2010: 464-468 - [c21]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP 2010: 1594-1597 - [c20]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS 2010: 466-469 - [c19]Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin:
Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS 2010: 531-534 - [c18]Cyrille Chavet, Philippe Coussy:
A memory mapping approach for parallel interleaver design with multiples read and write accesses. ISCAS 2010: 3168-3171 - [c17]Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin:
A Design Flow for Critical Embedded Systems. SIES 2010: 229-233 - [i7]Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard:
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. CoRR abs/1002.3990 (2010)
2000 – 2009
- 2009
- [j6]Philippe Coussy, Andrés Takach:
Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design. IEEE Des. Test Comput. 26(4): 4-6 (2009) - [j5]Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach:
An Introduction to High-Level Synthesis. IEEE Des. Test Comput. 26(4): 8-17 (2009) - [j4]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. 56(2-3): 167-186 (2009) - 2008
- [j3]Philippe Coussy, Ghizlane Lhairech-Lebreton, Dominique Heller:
Multiple Word-Length High-Level Synthesis. EURASIP J. Embed. Syst. 2008 (2008) - 2007
- [j2]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip. Integr. 40(2): 94-105 (2007) - [c16]Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy:
Synthesis of Multimode digital signal processing systems. AHS 2007: 318-325 - [c15]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO 2007: 846-850 - [c14]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO 2007: 1625-1629 - [c13]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI 2007: 347-352 - [c12]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611 - [c11]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS 2007: 2946-2949 - [i6]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. CoRR abs/0706.1692 (2007) - [i5]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A Design Methodology for Space-Time Adapter. CoRR abs/0706.2732 (2007) - [i4]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. CoRR abs/0706.2824 (2007) - [i3]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Application of a design space exploration tool to enhance interleaver generation. CoRR abs/0706.3009 (2007) - 2006
- [j1]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5(1): 29-53 (2006) - [c10]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS 2006: 244-249 - [i2]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006) - [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin:
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006) - 2005
- [c9]Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart:
SystemCmantic: A high level Modelling and Co-Design Framework. FDL 2005: 341-353 - [c8]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) 2005: 61-64 - [c7]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683 - 2004
- [c6]Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin:
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) 2004: 45-48 - 2003
- [c5]Philippe Coussy, Adel Baganne, Eric Martin:
Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC 2003: 38-43 - 2002
- [c4]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for integrating IP into SOC systems. CICC 2002: 307-310 - [c3]Philippe Coussy, Adel Baganne, Eric Martin:
IP cores integration in DSP System-on-chip designs. EUSIPCO 2002: 1-4 - [c2]Philippe Coussy, Adel Baganne, Eric Martin:
Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS 2002: 733-736 - [c1]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for IP integration. ISCAS (4) 2002: 711-714
Coauthor Index
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