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2020 – today
- 2024
[c34]Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran:
SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. DATE 2024: 1-6- 2023
- [j7]Jing Gong
, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran:
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3505-3518 (2023) - [c33]Siddhartha, Justin Tan, Rajesh Bansal, Huang Chee Cheun, Yuta Tokusashi, Chong Yew Kwan, Haris Javaid, Mario Baldi:
Demo: Enabling DNN Inference in the Network Data Plane. EuroP4@CoNEXT 2023: 65-68 - [i6]Guanwen Zhong, Aditya Kolekar, Burin Amornpaisannon, Inho Choi, Haris Javaid, Mario Baldi:
A Primer on RecoNIC: RDMA-enabled Compute Offloading on SmartNIC. CoRR abs/2312.06207 (2023) - 2022
- [c32]Rashmi Agrawal, Ji Yang, Haris Javaid:
Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains. ASAP 2022: 148-155 - [c31]Rashmi Agrawal, Ji Yang, Haris Javaid:
Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains. FPGA 2022: 50 - [c30]Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner:
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. ICDCS 2022: 258-268 - [c29]Nathania Santoso, Haris Javaid:
Improving Energy Efficiency of Permissioned Blockchains Using FPGAs. ICPADS 2022: 177-184 - [i5]Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran:
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. CoRR abs/2209.04161 (2022) - [i4]Nathania Santoso, Haris Javaid:
Improving Energy Efficiency of Permissioned Blockchains Using FPGAs. CoRR abs/2210.11839 (2022) - 2021
- [i3]Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner:
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. CoRR abs/2104.06968 (2021) - [i2]Rashmi Agrawal, Ji Yang, Haris Javaid:
Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains. CoRR abs/2112.02229 (2021) - 2020
- [j6]Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
Hardware Trojan Mitigation in Pipelined MPSoCs. ACM Trans. Design Autom. Electr. Syst. 25(1): 6:1-6:27 (2020) - [c28]Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
WEID: Worst-case Error Improvement in Approximate Dividers. ASP-DAC 2020: 593-598 - [c27]Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
REALM: Reduced-Error Approximate Log-based Integer Multiplier. DATE 2020: 1366-1371 - [c26]Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran:
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. VLSID 2020: 84-89
2010 – 2019
- 2019
- [c25]Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner:
FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. CVCBT 2019: 73-76 - [c24]Hassaan Saadat, Haris Javaid, Sri Parameswaran:
Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. DAC 2019: 161 - [c23]Haris Javaid, Chengchen Hu, Gordon J. Brebner:
Optimizing Validation Phase of Hyperledger Fabric. MASCOTS 2019: 269-275 - [i1]Haris Javaid, Chengchen Hu, Gordon J. Brebner:
Optimizing Validation Phase of Hyperledger Fabric. CoRR abs/1907.08367 (2019) - 2016
- [j5]Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran:
Switchable cache: utilising dark silicon for application specific cache optimisations. IET Comput. Digit. Tech. 10(4): 157-164 (2016) - 2015
- [j4]Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran:
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1991-2003 (2015) - [c22]Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
ADAPT: An adaptive manycore methodology for software pipelined applications. ASP-DAC 2015: 701-706 - [c21]Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
SuperNet: multimode interconnect architecture for manycore chips. DAC 2015: 85:1-85:6 - [c20]Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran:
E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE 2015: 363-368 - [c19]Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
Malleable NoC: dark silicon inspired adaptable Network-on-Chip. DATE 2015: 1245-1248 - 2014
- [b2]Haris Javaid, Sri Parameswaran:
Pipelined Multiprocessor System-on-Chip for Multimedia. Springer 2014, ISBN 978-3-319-01112-7, pp. I-VIII, 1-169 - [j3]Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 663-676 (2014) - [j2]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs). IEEE Trans. Parallel Distributed Syst. 25(8): 2159-2168 (2014) - [c18]Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran:
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. DAC 2014: 33:1-33:6 - [c17]Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. DAC 2014: 161:1-161:6 - [c16]Hong Chinh Doan, Haris Javaid, Sri Parameswaran:
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. DATE 2014: 1-6 - [c15]Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran:
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. DATE 2014: 1-6 - 2013
- [c14]Haris Javaid, Daniel Witono, Sri Parameswaran:
Multi-mode pipelined MPSoCs for streaming applications. ASP-DAC 2013: 231-236 - [c13]Su Myat Min, Haris Javaid, Sri Parameswaran:
RExCache: Rapid exploration of unified last-level cache. ASP-DAC 2013: 582-587 - [c12]Su Myat Min, Haris Javaid, Sri Parameswaran:
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. DAC 2013: 22:1-22:10 - [c11]Haseeb Bokhari, Haris Javaid, Sri Parameswaran:
System-level optimization of on-chip communication using express links for throughput constrained MPSoCs. ESTIMedia 2013: 68-77 - [c10]Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran:
Energy-aware synthesis of application specific MPSoCs. ICCD 2013: 62-69 - [c9]Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. MECO 2013: 42-45 - 2012
- [b1]Haris Javaid:
Analyses and Optimisations for Pipelined MPSoCs. University of New South Wales, Sydney, Australia, 2012 - 2011
- [c8]Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel:
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. DAC 2011: 1032-1037 - [c7]Hong Chinh Doan, Haris Javaid, Sri Parameswaran:
Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. ESTIMedia 2011: 56-65 - [c6]Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. ICCAD 2011: 616-623 - 2010
- [j1]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1777-1789 (2010) - [c5]Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran:
Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. CODES+ISSS 2010: 75-84 - [c4]Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran:
Rapid runtime estimation methods for pipelined MPSoCs. DATE 2010: 363-368 - [c3]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran:
Fidelity metrics for estimation models. ICCAD 2010: 1-8
2000 – 2009
- 2009
- [c2]Haris Javaid, Sri Parameswaran:
A design flow for application specific heterogeneous pipelined multiprocessor systems. DAC 2009: 250-253 - 2008
- [c1]Haris Javaid, Sri Parameswaran:
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. CODES+ISSS 2008: 1-6
Coauthor Index
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last updated on 2024-11-14 00:51 CET by the dblp team
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