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ORCIDLeendert M. Huisman
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2000 – 2009
- 2004
[j8]Leendert M. Huisman:
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 91-101 (2004)- [c12]Leendert M. Huisman, Maroun Kassab, Leah Pastel:
Data Mining Integrated Circuit Fails with Fail Commonalities. ITC 2004: 661-668 - 2003
- [c11]Peter Wohl, Leendert M. Huisman:
Analysis and Design of Optimal Combinational Compactors. VTS 2003: 101-106 - 2001
- [c10]Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski:
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. ITC 2001: 287-296
1990 – 1999
- 1998
- [c9]Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika:
Diagnosis and characterization of timing-related defects by time-dependent light emission. ITC 1998: 733-739 - [c8]Leendert M. Huisman:
Correlations between path delays and the accuracy of performance prediction. ITC 1998: 801-808 - 1995
- [j7]Leendert M. Huisman:
Yield fluctuations and defect models. J. Electron. Test. 7(3): 241-254 (1995) - 1994
- [j6]Leendert M. Huisman, Sandip Kundu:
Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distributed Syst. 5(1): 94-97 (1994) - [c7]Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman:
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. ITC 1994: 739-746 - 1992
- [c6]Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs. ITC 1992: 30-40 - 1991
- [c5]Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar:
Symbolic implication in test generation. EURO-DAC 1991: 492-496 - 1990
- [c4]Leendert M. Huisman, Raja Daoud:
Fault simulation of logic designs on parallel processors with distributed memory. ITC 1990: 690-697
1980 – 1989
- 1988
- [j5]Leendert M. Huisman:
The reliability of approximate testability measures. IEEE Des. Test 5(6): 57-67 (1988) - [j4]Larry Carter, Leendert M. Huisman, Tom W. Williams:
TRIM: testability range by ignoring the memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 38-49 (1988) - [j3]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 838-849 (1988) - 1986
- [c3]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis. DAC 1986: 164-170 - [c2]Leendert M. Huisman, Larry Carter, Tom W. Williams:
TRIM : Testability Range by Ignoring the Memory. ITC 1986: 474-479 - 1984
- [j2]Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Fast Pass-Transistor Simulation for Custom MOS Circuits. IEEE Des. Test 1(1): 71-81 (1984) - [j1]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman:
Using a Hardware Simulation Engine for Custom MOS Structured Designs. IBM J. Res. Dev. 28(5): 564-571 (1984) - 1983
- [c1]Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Simulating pass transistor circuits using logic simulation machines. DAC 1983: 157-163
Coauthor Index
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