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ORCIDMarcelo de Souza Moraes
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2010 – 2019
- 2012
[c4]Marcelo de Souza Moraes, Marcos Barcellos Hervé, Marcelo Lubaszewski:
Low pin count DfT technique for RFID ICs. DFT 2012: 31-36- 2011
- [j1]Marcos Barcellos Hervé, Marcelo de Souza Moraes, Pedro Almeida, Marcelo Lubaszewski, Fernanda Lima Kastensmidt
, Érika F. Cota:
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers. J. Electron. Test. 27(5): 635-646 (2011)
2000 – 2009
- 2006
- [c3]Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski:
Using a software testing technique to identify registers for partial scan implementation. SBCCI 2006: 208-213 - [c2]Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes:
Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions. VLSI-SoC 2006: 314-319 - 2005
- [c1]Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski:
A constraint-based solution for on-line testing of processors embedded in real-time applications. SBCCI 2005: 68-73
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last updated on 2025-01-09 00:54 CET by the dblp team
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