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2020 – today
- 2024
[j17]Emad Malekzadeh Arasteh
, Rainer Dömer:
Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention. ACM Trans. Embed. Comput. Syst. 23(5): 75:1-75:32 (2024)- [c70]Emad Malekzadeh Arasteh, Vivek Govindasamy, Rainer Dömer:
BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0. DATE 2024: 1-6 - 2023
- [c69]Vivek Govindasamy, Rainer Dömer:
Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells. FDL 2023: 1-8 - [c68]Lars Luchterhandt, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Mueller, Babak Sadiye:
Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. MBMV 2023: 1-7 - 2022
- [c67]Yutong Wang, Arya Daroui, Rainer Dömer:
Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0. IESS 2022: 65-77 - [c66]Vivek Govindasamy, Emad Malekzadeh Arasteh, Rainer Dömer:
Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells. IESS 2022: 101-112 - 2021
- [j16]Zhongqi Cheng, Tim Schmidt, Rainer Dömer:
Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation. Int. J. Parallel Program. 49(2): 200-215 (2021) - [c65]Rainer Dömer, Zhongqi Cheng, Daniel Mendoza, Emad Malekzadeh Arasteh:
Pushing the Limits of Parallel Discrete Event Simulation for SystemC. A Journey of Embedded and Cyber-Physical Systems 2021: 97-105 - [c64]Emad Malekzadeh Arasteh, Rainer Dömer:
Improving Parallelism in System Level Models by Assessing PDES Performance. FDL 2021: 1-7 - 2020
- [c63]Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dömer:
Event Delivery using Prediction for Faster Parallel SystemC Simulation. ASP-DAC 2020: 357-362 - [c62]Daniel Mendoza, Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dömer:
Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES. DATE 2020: 885-890
2010 – 2019
- 2019
- [j15]Zhongqi Cheng, Rainer Dömer:
Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models. ACM Trans. Embed. Comput. Syst. 18(5s): 79:1-79:20 (2019) - [c61]Emad Malekzadeh Arasteh, Rainer Dömer:
An Untimed SystemC Model of GoogLeNet. IESS 2019: 117-129 - 2018
- [c60]Tim Schmidt, Zhongqi Cheng, Rainer Dömer:
Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. DATE 2018: 349-354 - [c59]Zhongqi Cheng, Tim Schmidt, Rainer Dömer:
SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation. FDL 2018: 5-16 - 2017
- [c58]Tim Schmidt, Guantao Liu, Rainer Dömer:
Hybrid analysis of SystemC models for fast and accurate parallel simulation. ASP-DAC 2017: 226-231 - [c57]Tim Schmidt, Guantao Liu, Rainer Dömer:
Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation. DAC 2017: 79:1-79:6 - [c56]Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Dömer:
Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study. HLDVT 2017: 74-81 - [p3]Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya:
Introduction to Hardware/Software Codesign. Handbook of Hardware/Software Codesign 2017: 3-26 - [p2]Rainer Dömer, Guantao Liu, Tim Schmidt:
Parallel Simulation. Handbook of Hardware/Software Codesign 2017: 533-564 - [p1]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
SCE: System-on-Chip Environment. Handbook of Hardware/Software Codesign 2017: 1019-1050 - 2016
- [j14]Rainer Dömer:
Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation. IEEE Embed. Syst. Lett. 8(4): 81-84 (2016) - [c55]Guantao Liu, Tim Schmidt, Rainer Dömer:
A segment-aware multi-core scheduler for system C PDES. HLDVT 2016: 100-107 - [c54]Tim Schmidt, Guantao Liu, Rainer Dömer:
Automatic Generation of Thread Communication Graphs from SystemC Source Code. SCOPES 2016: 108-115 - 2015
- [c53]Guantao Liu, Tim Schmidt, Rainer Dömer, Ajit Dingankar, Desmond Kirkpatrick:
Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories. ASP-DAC 2015: 429-434 - [c52]Che-Wei Chang, Rainer Dömer:
Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories. ASP-DAC 2015: 606-611 - [c51]Che-Wei Chang, Rainer Dömer:
May-happen-in-parallel analysis of ESL models using UPPAAL model checking. DATE 2015: 1567-1570 - 2014
- [j13]Tim Schmidt, Kim Grüttner, Rainer Dömer, Achim Rettberg:
A program state machine based virtual processing model in SystemC. SIGBED Rev. 11(4): 7-12 (2014) - [j12]Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer:
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1859-1872 (2014) - [c50]Weiwei Chen, Xu Han, Rainer Dömer:
May-happen-in-parallel analysis based on segment graphs for safe ESL models. DATE 2014: 1-6 - [c49]Tim Schmidt, Kim Grüttner, Rainer Dömer, Achim Rettberg:
A Program State Machine Based Virtual Processing Model in SystemC. EWiLi 2014 - [c48]Yasaman Samei Syahkal, Rainer Dömer:
Powermonitor: a versatile API for automated power-aware ESL design. FDL 2014: 1-4 - [c47]Yasaman Samei Syahkal, Rainer Dömer:
Automated estimation of power consumption for rapid system level design. IPCCC 2014: 1-8 - 2013
- [j11]Weiwei Chen, Xu Han, Che-Wei Chang, Rainer Dömer:
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. IEEE Des. Test 30(1): 45-54 (2013) - [c46]Weiwei Chen, Rainer Dömer:
Optimized out-of-order parallel discrete event simulation using predictions. DATE 2013: 3-8 - [c45]Takuya Azumi, Yasaman Samei Syahkal, Yuko Hara-Azumi, Hiroshi Oyama, Rainer Dömer:
TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component. IESS 2013: 1-13 - [c44]Che-Wei Chang, Rainer Dömer:
Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories. IESS 2013: 116-127 - [c43]Xu Han, Weiwei Chen, Rainer Dömer:
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. M-SCOPES 2013: 40-47 - 2012
- [j10]Pramod Chandraiah, Rainer Dömer:
Computer-Aided Recoding to Create Structured and Analyzable System Models. ACM Trans. Embed. Comput. Syst. 11(S1): 23 (2012) - [c42]Rainer Dömer, Weiwei Chen, Xu Han:
Parallel discrete event simulation of Transaction Level Models. ASP-DAC 2012: 227-231 - [c41]Weiwei Chen, Rainer Dömer:
An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation. ASP-DAC 2012: 461-466 - [c40]Weiwei Chen, Xu Han, Rainer Dömer:
Out-of-order parallel simulation for ESL design. DATE 2012: 141-146 - [c39]Weiwei Chen, Che-Wei Chang, Xu Han, Rainer Dömer:
Eliminating race conditions in system-level models by using parallel simulation infrastructure. HLDVT 2012: 118-123 - 2011
- [j9]Weiwei Chen, Xu Han, Rainer Dömer:
Multicore Simulation of Transaction-Level Models Using the SoC Environment. IEEE Des. Test Comput. 28(3): 20-31 (2011) - [c38]Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer:
Multi-core parallel simulation of System-level Description Languages. ASP-DAC 2011: 311-316 - 2010
- [j8]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Fast and accurate processor models for efficient MPSoC design. ACM Trans. Design Autom. Electr. Syst. 15(2): 10:1-10:26 (2010) - [c37]Weiwei Chen, Rainer Dömer:
A fast heuristic scheduling algorithm for periodic ConcurrenC models. ASP-DAC 2010: 161-166 - [c36]Rainer Dömer:
Computer-aided recoding for multi-core systems. ASP-DAC 2010: 713-716 - [c35]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
System-level development of embedded software. ASP-DAC 2010: 903-909 - [c34]Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jürgen Mössinger, Andreas von Schwerin:
Panel Session - Who Is Closing the embedded software design gap? DATE 2010: 932 - [c33]Weiwei Chen, Xu Han, Rainer Dömer:
ESL design and multi-core validation using the System-on-Chip Environment. HLDVT 2010: 142-147
2000 – 2009
- 2009
- [c32]Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. ASP-DAC 2009: 290-292 - [c31]Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl:
Programming MPSoC platforms: Road works ahead! DATE 2009: 1584-1589 - [c30]Ines Viskic, Rainer Dömer:
A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance. IESS 2009: 44-56 - [c29]Weiwei Chen, Rainer Dömer:
ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs. IESS 2009: 57-65 - [c28]Rainer Dömer:
Efficient Modeling of Embedded Systems Using Computer-Aided Recoding. IESS 2009: 310-311 - 2008
- [j7]Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski:
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008) - [j6]Pramod Chandraiah, Rainer Dömer:
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1078-1090 (2008) - [j5]Gunar Schirner, Rainer Dömer:
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Trans. Embed. Comput. Syst. 8(1): 4:1-4:29 (2008) - [j4]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 466-475 (2008) - [c27]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. ASP-DAC 2008: 271-276 - [c26]Pramod Chandraiah, Rainer Dömer:
Automatic re-coding of reference code into structured and analyzable SoC models. ASP-DAC 2008: 440-445 - [c25]Gunar Schirner, Rainer Dömer:
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. DATE 2008: 122-127 - 2007
- [j3]Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1676-1687 (2007) - [j2]Gunar Schirner, Rainer Dömer:
Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1688-1699 (2007) - [c24]Pramod Chandraiah, Junyu Peng, Rainer Dömer:
Creating Explicit Communication in SoC Models Using Interactive Re-Coding. ASP-DAC 2007: 50-55 - [c23]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. ASP-DAC 2007: 384-389 - [c22]Pramod Chandraiah, Rainer Dömer:
Pointer re-coding for creating definitive MPSoC models. CODES+ISSS 2007: 33-38 - [c21]Pramod Chandraiah, Rainer Dömer:
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. DAC 2007: 787-790 - [c20]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144 - [c19]Pramod Chandraiah, Rainer Dömer:
An Interactive Model Re-Coder for Efficient SoC Specification. IESS 2007: 193-206 - [c18]Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer:
Embedded Software Development in a System-Level Design Flow. IESS 2007: 289-298 - [e1]Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig:
Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA. IFIP Advances in Information and Communication Technology 231, Springer 2007, ISBN 978-0-387-72257-3 [contents] - 2006
- [c17]Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69 - [c16]Gunar Schirner, Rainer Dömer:
Accurate yet fast modeling of real-time communication. CODES+ISSS 2006: 70-75 - [c15]Gunar Schirner, Rainer Dömer:
Quantitative analysis of transaction level models for the AMBA bus. DATE 2006: 230-235 - [c14]Ines Viskic, Rainer Dömer:
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. DSD 2006: 288-294 - [c13]Gunar Schirner, Rainer Dömer:
Fast and accurate transaction level models using result oriented modeling. ICCAD 2006: 363-368 - 2005
- [c12]Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48 - [c11]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260 - [c10]Haobo Yu, Rainer Dömer, Daniel D. Gajski:
Software and Driver Synthesis from Transaction Level Models. IESS 2005: 65-76 - [c9]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic Generation of Communication Architectures. IESS 2005: 179-188 - [c8]Gunar Schirner, Rainer Dömer:
Abstract Communication Modeling. IESS 2005: 189-200 - 2004
- [c7]Haobo Yu, Rainer Dömer, Daniel Gajski:
Embedded software generation from system level design languages. ASP-DAC 2004: 463-468 - 2002
- [c6]Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
The Formal Execution Semantics of SpecC. ISSS 2002: 150-155 - 2001
- [b2]Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski:
System Design - A Practical Guide with SpecC. Springer 2001, ISBN 978-0-7923-7387-2, pp. 1-255 - 2000
- [b1]Rainer Dömer:
System-level modeling and design with the SpecC language. Technical University of Dortmund, Germany, 2000, pp. 1-214 - [c5]Rainer Dömer, Daniel Gajski:
Reuse and protection of intellectual property in the SpecC system. ASP-DAC 2000: 49-54
1990 – 1999
- 1998
- [j1]Rainer Dömer, Daniel D. Gajski, Jianwen Zhu:
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40(3): 7-12 (1998) - [c4]Daniel Gajski, Rainer Dömer, Jianwen Zhu:
IP-Centric Methodology and Specification Language. DIPES 1998: 3-22 - 1997
- [c3]Peter Marwedel, Birger Landwehr, Rainer Dömer:
Built-in chaining: introducing complex components into architectural synthesis. ASP-DAC 1997: 599-605 - 1996
- [c2]Peter Marwedel, Steven Bashford, Rainer Dömer, Birger Landwehr, Ingolf Markhof:
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis. ED&TC 1996: 600 - 1994
- [c1]Birger Landwehr, Peter Marwedel, Rainer Dömer:
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. EURO-DAC 1994: 90-95
Coauthor Index
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last updated on 2024-10-04 21:00 CEST by the dblp team
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