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2010 – 2019
- 2014
[c56]Kaituo Li, Pallavi Joshi, Aarti Gupta
, Malay K. Ganai:
ReproLite: A Lightweight Tool to Quickly Reproduce Hard System Bugs. SoCC 2014: 25:1-25:13- [c55]Yu Lin, Franjo Ivancic, Pallavi Joshi, Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta:
Environment-Sensitive Performance Tuning for Distributed Service Orchestration. VECPAR 2014: 209-223 - [e2]Malay K. Ganai, Alper Sen:
Proceedings of the Second International Workshop on Design and Implementation of Formal Tools and Systems, Portland, OR, USA, October 19, 2013. CEUR Workshop Proceedings 1130, CEUR-WS.org 2014 [contents] - 2013
- [c54]Malay K. Ganai:
Efficient data race prediction with incremental reasoning on time-stamped lock history. ASE 2013: 37-47 - [c53]Pallavi Joshi, Malay K. Ganai, Gogul Balakrishnan, Aarti Gupta, Nadia Papakonstantinou:
SETSUDŌ: perturbation-based testing framework for scalable distributed systems. TRIOS@SOSP 2013: 7:1-7:14 - 2012
- [c52]Malay K. Ganai:
Dynamic Livelock Analysis of Multi-threaded Programs. RV 2012: 3-18 - [c51]Malay K. Ganai, Dongyoon Lee, Aarti Gupta:
DTAM: dynamic taint analysis of multi-threaded programs for relevancy. SIGSOFT FSE 2012: 46 - [e1]Malay K. Ganai, Armin Biere:
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, Austin, USA, November 3, 2011. CEUR Workshop Proceedings 832, CEUR-WS.org 2012 [contents] - 2011
- [j7]Chao Wang, Sudipta Kundu, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta:
Symbolic predictive analysis for concurrent programs. Formal Aspects Comput. 23(6): 781-805 (2011) - [c50]Malay K. Ganai:
Scalable and precise symbolic analysis for atomicity violations. ASE 2011: 123-132 - [c49]Malay K. Ganai, Nipun Arora, Chao Wang, Aarti Gupta, Gogul Balakrishnan:
BEST: A symbolic testing tool for predicting multi-threaded program failures. ASE 2011: 596-599 - [c48]Chao Wang, Malay K. Ganai:
Predicting Concurrency Failures in the Generalized Execution Traces of x86 Executables. RV 2011: 4-18 - 2010
- [c47]Sudipta Kundu, Malay K. Ganai, Chao Wang:
Contessa: Concurrency Testing Augmented with Symbolic Analysis. CAV 2010: 127-131 - [c46]Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke:
Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems. FMCAD 2010: 81-89 - [c45]Malay K. Ganai:
Propelling SAT and SAT-based BMC using careset. FMCAD 2010: 231-238 - [c44]Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang:
Scalable and precise program analysis at NEC. FMCAD 2010: 273-274 - [c43]Malay K. Ganai, Chao Wang, Weihong Li:
Efficient state space exploration: Interleaving stateless and state-based model checking. ICCAD 2010: 786-793 - [c42]Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta:
Numerical stability analysis of floating-point computations using software model checking. MEMOCODE 2010: 49-58 - [c41]Malay K. Ganai, Chao Wang:
Interval Analysis for Concurrent Trace Programs Using Transaction Sequence Graphs. RV 2010: 253-269 - [c40]Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta:
Trace-Based Symbolic Analysis for Atomicity Violations. TACAS 2010: 328-342
2000 – 2009
- 2009
- [c39]Chao Wang, Sudipta Kundu, Malay K. Ganai, Aarti Gupta:
Symbolic Predictive Analysis for Concurrent Programs. FM 2009: 256-272 - [c38]Malay K. Ganai, Franjo Ivancic:
Efficient decision procedure for non-linear arithmetic constraints using CORDIC. FMCAD 2009: 61-68 - [c37]Malay K. Ganai, Weihong Li:
Bang for the buck: Improvising and scheduling verification engines for effective resource utilization. MEMOCODE 2009: 8-17 - [c36]Malay K. Ganai, Sudipta Kundu:
Reduction of Verification Conditions for Concurrent System Using Mutually Atomic Transactions. SPIN 2009: 68-87 - 2008
- [j6]Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1513-1517 (2008) - [j5]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008) - [c35]Malay K. Ganai, Aarti Gupta:
Tunneling and slicing: towards scalable BMC. DAC 2008: 137-142 - [c34]Sudipta Kundu, Malay K. Ganai, Rajesh Gupta:
Partial order reduction for scalable testing of systemC TLM designs. DAC 2008: 936-941 - [c33]Malay K. Ganai, Aarti Gupta:
Completeness in SMT-based BMC for Software Programs. DATE 2008: 831-836 - [c32]Malay K. Ganai:
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT(). Haifa Verification Conference 2008: 68-83 - [c31]Malay K. Ganai, Weihong Li:
d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework. Haifa Verification Conference 2008: 194-199 - [c30]Chao Wang, Malay K. Ganai, Shuvendu K. Lahiri, Daniel Kroening:
Embedded software verification: challenges and solutions. ICCAD 2008: 5 - [c29]Gogul Balakrishnan, Malay K. Ganai:
PED: Proof-Guided Error Diagnosis by Triangulation of Program Error Causes. SEFM 2008: 268-278 - [c28]Malay K. Ganai, Aarti Gupta:
Efficient Modeling of Concurrent Systems in BMC. SPIN 2008: 114-133 - 2007
- [b1]Malay K. Ganai, Aarti Gupta:
SAT-Based Scalable Formal Verification Solutions. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-69166-4, pp. 1-326 - [j4]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta:
SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic. J. Satisf. Boolean Model. Comput. 3(1-2): 91-114 (2007) - [c27]Malay K. Ganai, Aarti Gupta:
Efficient BMC for Multi-Clock Systems with Clocked Specifications. ASP-DAC 2007: 310-315 - [c26]Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi:
Synthesizing "Verification Aware" Models: Why and How? VLSI Design 2007: 50-56 - [i1]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. CoRR abs/0710.4666 (2007) - 2006
- [j3]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient distributed SAT and SAT-based distributed Bounded Model Checking. Int. J. Softw. Tools Technol. Transf. 8(4-5): 387-396 (2006) - [c25]Chao Wang, Aarti Gupta, Malay K. Ganai:
Predicate learning and selective theory deduction for a difference logic solver. DAC 2006: 235-240 - [c24]Malay K. Ganai, Aarti Gupta:
Accelerating high-level bounded model checking. ICCAD 2006: 794-801 - [c23]Aarti Gupta, Malay K. Ganai, Chao Wang:
SAT-Based Verification Methods and Applications in Hardware Verification. SFM 2006: 108-143 - [c22]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta:
SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver. TACAS 2006: 135-150 - 2005
- [c21]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar:
F-Soft: Software Verification Platform. CAV 2005: 301-306 - [c20]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Beyond safety: customized SAT-based model checking. DAC 2005: 738-743 - [c19]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101 - [c18]Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai, Vineet Kahlon, Chao Wang, Zijiang Yang:
Model Checking C Programs Using F-SOFT. ICCD 2005: 297-308 - [c17]Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta:
Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination. LPAR 2005: 322-336 - [c16]Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai:
Localization and Register Sharing for Predicate Abstraction. TACAS 2005: 397-412 - [c15]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580 - [c14]Aarti Gupta, Malay K. Ganai, Pranav Ashar:
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188 - 2004
- [c13]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452 - [c12]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517 - [c11]Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang:
Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164 - 2003
- [c10]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209 - [c9]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347 - [c8]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829 - [c7]Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar:
Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423 - 2002
- [j2]Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai:
Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1377-1394 (2002) - [c6]Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik:
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750 - [c5]Malay K. Ganai, Adnan Aziz:
Improved SAT-Based Bounded Reachability Analysis. ASP-DAC/VLSI Design 2002: 729-734 - 2001
- [j1]Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal:
SIVA: A System for Coverage-Directed State Space Search. J. Electron. Test. 17(1): 11-27 (2001) - [c4]Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi:
Circuit-based Boolean Reasoning. DAC 2001: 232-237 - [c3]Malay K. Ganai, Adnan Aziz:
Rarity based guided state space search. ACM Great Lakes Symposium on VLSI 2001: 97-102
1990 – 1999
- 1999
- [c2]Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann:
Enhancing Simulation with BDDs and ATPG. DAC 1999: 385-390 - [c1]Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns:
Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377
Coauthor Index
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