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ORCIDBich-Yen Nguyen
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2020 – today
- 2024
[c17]Xuanqi Chen, Gan Liu, Wei Shi, Yuye Kang, Qiwen Kong, Yuxuan Wang, Rui Shao, Bich-Yen Nguyen, Gengchiau Liang, Kaizhen Han, Xiao Gong:
Fluorine Plasma Treatment-Enabled ITO Transistors: Excellent Reliability and Comprehensive Understanding of Temperature Dependence from 77K to 375K. VLSI Technology and Circuits 2024: 1-2- [c16]Gan Liu, Qiwen Kong, Zuopu Zhou, X. Ying, Chen Sun, Kaizhen Han, Yuye Kang, Dong Zhang, Xiaolin Wang, Yang Feng, Wei Shi, Bich-Yen Nguyen, N. Kai, Gengchiau Liang, Xiao Gong:
Unveiling the Impact of AC PBTI on Hydrogen Formation in Oxide Semiconductor Transistors. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c15]Zuopu Zhou, Leming Jiao, Qiwen Kong, Zijie Zheng, Kaizhen Han, Yue Chen, Chen Sun, Bich-Yen Nguyen, Xiao Gong:
Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F2 High-Density Integration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c14]Guillaume Besnard, Bich-Yen Nguyen, Christophe Maleville:
Smart Cut™ technology: from Substrate Enginnering to Advanced 3D Integration. ICICDT 2022: 81-83 - [c13]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo
, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi:
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331
2010 – 2019
- 2019
- [c12]Walter Schwarzenbach, L. Loubriat, Vincent Joseph, Laurent Viravaux, Olivier Moreau, Sebastien Lasserre, Bich-Yen Nguyen:
22FD-SOI Variability Improvement Thanks to SmartCut Thickness Control at Atomic Scale. ESSDERC 2019: 64-65 - [c11]Walter Schwarzenbach, Bich-Yen Nguyen, Guillaume Besnard:
Low Temperature SmartCutTM enables High Density 3D SoC Applications. ICICDT 2019: 1-2 - 2018
- [c10]Yiming Qu, Ran Cheng, Wei Liu, Junkang Li, Bich-Yen Nguyen, Olivier Faynot, Nuo Xu, Bing Chen, Yi Zhao:
Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs. IRPS 2018: 6 - 2017
- [c9]Eunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen:
Layout engineering to suppress hysteresis of negative capacitance FinFET. ICICDT 2017: 1-3 - [c8]Walter Schwarzenbach, Manuel Sellier, Bich-Yen Nguyen, Christophe Girard, Christophe Maleville:
FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond. ICICDT 2017: 1-2 - 2015
- [c7]Ionut Radu, Bich-Yen Nguyen, Gweltaz Gaudin, Carlos Mazure:
3D monolithic integration: Stacking technology and applications. ICICDT 2015: 1-3 - 2012
- [c6]Walter Schwarzenbach, N. Daval, S. Kerdiles, G. Chabanne, C. Figuet, S. Guerroudj, O. Bonnin, X. Cauchy, Bich-Yen Nguyen, Christophe Maleville:
Strained silicon on insulator substrates for fully depleted application. ICICDT 2012: 1-4 - 2010
- [c5]Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen, Walter Schwarzenbach, Cécile Moulin:
FDSOI: From substrate to devices and circuit applications. ESSCIRC 2010: 45-51 - [c4]Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Béranger, Marie-Anne Jaud, J. Dura, P. Perreau, Frédéric Boeuf, François Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara:
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. ISCAS 2010: 1703-1706 - [c3]Borivoje Nikolic, Changhwan Shin, Min Hee Cho, Xin Sun, Tsu-Jae King Liu, Bich-Yen Nguyen:
SRAM design in fully-depleted SOI technology. ISCAS 2010: 1707-1710
2000 – 2009
- 2009
- [c2]Claire Fenouillet-Béranger, P. Perreau, S. Denorme, L. Tosti, François Andrieu, Olivier Weber, S. Barnola, C. Arvet, Y. Campidelli, Sébastien Haendler, R. Beneyton, C. Perrot, C. de Buttet, P. Gros, Loan Pham-Nguyen, F. Leverd, P. Gouraud, F. Abbate, F. Baron, A. Torres, C. Laviron, L. Pinzelli, J. Vetier, C. Borowiak, A. Margain, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Olivier Faynot, Thomas Skotnicki:
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. ESSCIRC 2009: 88-91 - 2005
- [c1]Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen:
Physics-based compact modeling for nonclassical CMOS. ICCAD 2005: 211-216
Coauthor Index
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