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ORCIDHao Zheng 0005
Person information
- affiliation: University of Central Florida, Department of Electrical and Computer Engineering, Orlando, FL, USA
- affiliation (former, PhD): George Washington University, Department of Electrical and Computer Engineering, Washington, DC, USA
Other persons with the same name
- Hao Zheng — disambiguation page
- Hao Zheng 0001
![[0000-0002-8627-0591]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-8627-0591")
(aka: Hank Jayne) — University of South Florida, Tampa, FL, USA (and 1 more) - Hao Zheng 0002 — Georgia Institute of Technology, Atlanta, GA, USA
- Hao Zheng 0003 — Google (and 1 more)
- Hao Zheng 0004 — Xi'an Jiaotong University, School of Electronics and Information Engineering, China
- Hao Zheng 0006 — University of Louisiana at Lafayette, LA, USA (and 2 more)
- Hao Zheng 0007 — Xidian University, National Laboratory of Radar Signal Processing, China (and 1 more)
- Hao Zheng 0008 — Shanghai Jiao Tong University, Institute of Image Processing and Pattern Recognition, Institute of Medical Robotics, China
Other persons with a similar name
- Zheng-Hao Chong
- Zheng Hao — disambiguation page
- Zheng-Dong Hao
- Zheng-Hao Hong
- Hao-Zheng Li
- Dong Hao Zheng
- Hao-Dong Zheng
- Hao-Yuan Zheng
- Wenhao Zheng (aka: Wen-Hao Zheng) — disambiguation page
- Zi-Hao Zheng
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2020 – today
- 2024
[j9]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. 35(2): 349-361 (2024)- [j8]Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri:
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. 9(2): 115-127 (2024) - [c20]Sven Thijssen, Muhammad Rashedul Haq Rashed, Hao Zheng, Sumit Kumar Jha, Rickard Ewetz:
Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms. ASPDAC 2024: 812-817 - [c19]Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng:
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. DAC 2024: 274:1-274:6 - [c18]Fangzhou Ye, Lingxiang Yin, Amir Ghazizadeh Ahsaei, Hao Zheng:
EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization. DAC 2024: 304:1-304:6 - [c17]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. IPDPS 2024: 890-902 - [c16]Md Hafizul Islam Chowdhuryy, Hao Zheng, Fan Yao:
MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata. ISCA 2024: 693-707 - [c15]Jiaqi Xue, Yancheng Zhang, Yanshan Wang, Xueqiang Wang, Hao Zheng, Qian Lou:
CryptoTrain: Fast Secure Training on Encrypted Dataset. LAMPS@CCS 2024: 97-104 - [c14]Lingxiang Yin, Sanjay Gandham, Mingjie Lin, Hao Zheng:
SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks. MICRO 2024: 580-593 - 2023
- [j7]Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri:
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. J. Comput. Sci. Technol. 38(1): 115-127 (2023) - [c13]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. DAC 2023: 1-6 - [c12]Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin:
OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference. FCCM 2023: 225 - [c11]Lingxiang Yin, Jun Wang, Hao Zheng:
Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework. ACM Great Lakes Symposium on VLSI 2023: 489-495 - [c10]Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin:
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance. ICCAD 2023: 1-9 - [c9]Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz:
Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications. ICCAD 2023: 1-9 - [c8]Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng:
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. ICCAD 2023: 1-9 - [c7]Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng:
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. ICCD 2023: 166-169 - [c6]Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang:
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations. ISCA 2023: 48:1-48:12 - 2022
- [j6]Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth:
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2730-2741 (2022) - [j5]Hao Zheng, Ahmed Louri:
Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. IEEE Trans. Emerg. Top. Comput. 10(1): 223-236 (2022) - [j4]Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri:
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. 33(11): 2834-2845 (2022) - [j3]Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri:
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. 7(3): 709-723 (2022) - [c5]Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri:
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE 2022: 849-854 - [c4]Jiaqi Yang, Hao Zheng, Ahmed Louri:
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. ACM Great Lakes Symposium on VLSI 2022: 287-292 - 2021
- [c3]Hao Zheng, Ke Wang, Ahmed Louri:
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA 2021: 723-735 - 2020
- [j2]Ke Wang, Hao Zheng, Ahmed Louri:
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro 40(5): 56-63 (2020) - [c2]Hao Zheng, Ke Wang, Ahmed Louri:
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC 2020: 1-6
2010 – 2019
- 2019
- [c1]Hao Zheng, Ahmed Louri:
An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. DAC 2019: 47 - 2018
- [j1]Hao Zheng, Ahmed Louri:
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. IEEE Comput. Archit. Lett. 17(1): 88-91 (2018)
Coauthor Index
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