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Alessio Di Pasquo

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2024
[c3]
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  dblp key:
  - conf/vlsit/NaniMGBAACPFGGB24
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Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, D. Albano, C. Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, D. Burgos, Gabriele Minoia, P. Rossi, Marco Sosio, L. Vignoli, Enrico Temporiti, S. Scouten, S. Jantzi:
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. VLSI Technology and Circuits 2024: 1-2
2021
[c2]
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Alessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci:
Delay-lines jitter modeling and efficiency analysis in FinFET technology. ICECS 2021: 1-5
[c1]
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Alessio Di Pasquo, Claudio Nani, Enrico Monaco, Luca Fanucci:
A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC. ISCAS 2021: 1-5

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