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ORCIDRajiv A. Ravindran
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2000 – 2009
- 2007
[b1]Rajiv A. Ravindran:
Hardware/software techniques for memory power optimizations in embedded processors. University of Michigan, USA, 2007- [c8]Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke:
Compiler-managed partitioned data caches for low power. LCTES 2007: 237-247 - [c7]Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke:
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. MICRO 2007: 369-380 - 2005
- [j3]Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown:
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers 54(8): 998-1012 (2005) - [c6]Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown:
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. CGO 2005: 179-190 - 2004
- [j2]Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke:
Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. IEEE Micro 24(3): 10-20 (2004) - [c5]Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke:
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. CGO 2004: 201-212 - 2003
- [c4]Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke:
Systematic Register Bypass Customization for Application-Specific Processors. ASAP 2003: 64-74 - [c3]Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown:
Increasing the number of effective registers in a low-power processor using a windowed register file. CASES 2003: 125-136 - 2001
- [j1]Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
:
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1355-1371 (2001) - [c2]Rajiv A. Ravindran, Rajat Moona:
Retargetable Cache Simulation Using High Level Processor Models. ACSAC 2001: 114-129 - [c1]Rajiv A. Ravindran, Rajat Moona:
Retargetable Program Profiling Using High Level Processor Models. HiPC 2001: 224-236
Coauthor Index
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