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ORCIDHeng Yu 0001
Person information
- affiliation: University of Nottingham Ningbo China, Ningbo, China
Other persons with the same name
- Heng Yu — disambiguation page
- Heng Yu 0002
![[0000-0003-4391-7233]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-4391-7233")
— Pingdingshan University, Pingdingshan, China - Heng Yu 0003 — Shanghai Jiao Tong University, Shanghai, China
- Heng Yu 0004 — Ningbo University, Ningbo, China
- Heng Yu 0005 — Tsinghua University, Institute for Network Sciences and Cyberspace, Beijing, China
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2020 – today
- 2024
[j13]Fangcheng Guo, Jingjin Li, Chung Ket Thein, Anqi Gao, Jianfeng Ren, Chang Heon Lee, Jiawei Li, Tianxiang Cui, Heng Yu:
A scenario-customizable and visual-rendering simulator for on-vehicle vibration energy harvesting. Sustain. Comput. Informatics Syst. 44: 101039 (2024)- [c21]Chengtai Li, Yuting He, Jianfeng Ren, Ruibin Bai, Yitian Zhao, Heng Yu, Xudong Jiang:
Regression Residual Reasoning with Pseudo-labeled Contrastive Learning for Uncovering Multiple Complex Compositional Relations. IJCAI 2024: 3466-3474 - 2023
- [j12]Jiacheng Ying, Can Tong, Zehua Sheng, Bo-Wen Yao, Si-Yuan Cao, Heng Yu, Hui-Liang Shen:
Region-aware RGB and near-infrared image fusion. Pattern Recognit. 142: 109717 (2023) - [j11]Yicun Duan, Jianfeng Ren, Heng Yu, Xudong Jiang:
GAN-in-GAN for Monaural Speech Enhancement. IEEE Signal Process. Lett. 30: 853-857 (2023) - [j10]Weixiong Jiang, Heng Yu, Yajun Ha:
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1532-1545 (2023) - [j9]Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha:
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2952-2965 (2023) - [j8]Rui Li, Heng Yu, Lin Li, Yajun Ha:
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3881-3894 (2023) - [c20]Xinzhe Liu, Jianwen Luo, David Blinder, Fupeng Chen, Heng Yu, Peter Schelkens, Francky Catthoor, Yajun Ha:
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder. ICECS 2023: 1-4 - [c19]Qixing Zhang, Hao Sun, Qi Deng, Heng Yu, Yajun Ha:
NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction. ICECS 2023: 1-4 - 2022
- [j7]Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha:
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4873-4886 (2022) - [j6]Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha:
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 502-514 (2022) - [c18]Yuting He, Jiahui Meng, Chang Heon Lee, Jianfeng Ren, Jingjin Li, Qingyu Yang, Liyu Cai, Heng Yu:
Efficient and Accurate Feature Extraction Using Local Density Detector. AIPR 2022: 531-536 - [c17]Ruxin Ding, Jianfeng Ren, Heng Yu, Jiawei Li:
Dynamic Texture Recognition Using PDV Hashing and Dictionary Learning on Multi-Scale Volume Local Binary Pattern. ICASSP 2022: 1840-1844 - 2021
- [j5]Heng Yu, Yajun Ha, Bharadwaj Veeravalli, Fupeng Chen, Hesham El-Sayed:
DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return. IEEE Trans. Computers 70(5): 803-816 (2021) - [c16]Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha:
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. DAC 2021: 1027-1032 - [c15]Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha:
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. ISCAS 2021: 1-5 - [i1]Ruxin Ding, Jianfeng Ren, Heng Yu, Jiawei Li:
Dynamic Texture Recognition using PDV Hashing and Dictionary Learning on Multi-scale Volume Local Binary Pattern. CoRR abs/2111.12315 (2021) - 2020
- [j4]Chang Heon Lee, Heng Yu:
The impact of language on retweeting during acute natural disasters: uncertainty reduction and language expectancy perspectives. Ind. Manag. Data Syst. 120(8): 1501-1519 (2020) - [j3]Fupeng Chen, Heng Yu, Yajun Ha:
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles. ACM Trans. Embed. Comput. Syst. 19(2): 10:1-10:24 (2020) - [c14]Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha:
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. DAC 2020: 1-6 - [c13]Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha:
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c12]Weixiong Jiang, Heng Yu, Xinzhe Liu, Yajun Ha:
Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS. ICECS 2019: 446-449 - [c11]Weixiong Jiang, Heng Yu, Yajun Ha:
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC. SoCC 2019: 56-61 - 2017
- [j2]Hesham El-Sayed, Sharmi Sankar, Heng Yu, Gokulnath Thandavarayan:
Benchmarking of Recommendation Trust Computation for Trust/Trustworthiness Estimation in HDNs. Int. J. Comput. Commun. Control 12(5): 612-630 (2017) - [c10]Heng Yu, Yajun Ha, Jing Wang:
Quality Optimization of Resilient Applications under Temperature Constraints. Conf. Computing Frontiers 2017: 9-16 - 2014
- [c9]Heng Yu, Rizwan Syed, Yajun Ha:
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. DATE 2014: 1-6 - 2013
- [j1]Heng Yu, Yajun Ha, Bharadwaj Veeravalli:
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems. IEEE Trans. Computers 62(10): 2026-2040 (2013) - [c8]Heng Yu, Bharadwaj Veeravalli, Yajun Ha, Shaobo Luo:
Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors. CSE 2013: 770-777 - [c7]Junsong Hou, Heng Yu, Yajun Ha, Xin Liu:
The architecture and placement algorithm for a uni-directional routing based 3D FPGA. FPT 2013: 28-33 - 2012
- [c6]Michael Glaß, Heng Yu, Felix Reimann, Jürgen Teich:
Cross-Level Compositional Reliability Analysis for Embedded Systems. SAFECOMP 2012: 111-124 - 2010
- [c5]Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. DAC 2010: 493-498 - [c4]Heng Yu, Yajun Ha, Bharadwaj Veeravalli:
Communication-aware application mapping and scheduling for NoC-based MPSoCs. ISCAS 2010: 3232-3235
2000 – 2009
- 2009
- [c3]Guolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang:
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. ERSA 2009: 267-270 - 2008
- [c2]Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. ASP-DAC 2008: 452-455 - [c1]Yanhui Li, Shakith Fernando, Heng Yu, Xiaolei Chen, Yajun Ha, Teng Tiow Tay:
Tighter WCET analysis of input dependent programs with classified-cache memory architecture. ICECS 2008: 410-413
Coauthor Index
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