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ORCIDEhsan Atoofian
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2020 – today
- 2024
[j23]Sohrab Sajadimanesh
, Hanieh Aghaee Rad, Jean Paul Latyr Faye, Ehsan Atoofian:
Inexact Quantum Square Root Circuit for NISQ Devices. IEEE Access 12: 125856-125870 (2024)- [j22]Mohammad Hafezan, Ehsan Atoofian:
Improving Energy-Efficiency of Capsule Networks on Modern GPUs. IEEE Comput. Archit. Lett. 23(1): 49-52 (2024) - [j21]Mohammad Hafezan, Ehsan Atoofian:
Transient Fault Detection in Tensor Cores for Modern GPUs. ACM Trans. Embed. Comput. Syst. 23(5): 82:1-82:29 (2024) - [c42]Mohammad Hafezan, Reza Jahadi, Ehsan Atoofian:
PCTC: Hardware and Software Co-design for Pruned Capsule Networks on Tensor Cores. Euro-Par (2) 2024: 196-210 - [c41]Ehsan Atoofian:
Hardened-TC: A Low-cost Reliability Solution for CNNs Run by Modern GPUs. SOCC 2024: 1-6 - 2023
- [j20]Ehsan Atoofian:
PTTS: Power-aware tensor cores using two-sided sparsity. J. Parallel Distributed Comput. 173: 70-82 (2023) - [j19]Sohrab Sajadimanesh, Ehsan Atoofian:
EAM: Ensemble of approximate multipliers for robust DNNs. Microprocess. Microsystems 98: 104800 (2023) - 2022
- [c40]Sohrab Sajadimanesh, Jean Paul Latyr Faye, Ehsan Atoofian:
Practical approximate quantum multipliers for NISQ devices. CF 2022: 121-130 - [c39]Ehsan Atoofian:
Increasing Robustness against Adversarial Attacks through Ensemble of Approximate Multipliers. NAS 2022: 1-8 - [c38]Sohrab Sajadimanesh, Jean Paul Latyr Faye, Ehsan Atoofian:
NISQ-Friendly Non-Linear Activation Functions for Quantum Neural Networks. NAS 2022: 1-8 - 2021
- [j18]Ehsan Atoofian:
Trivial Bypassing in GPGPUs. IEEE Embed. Syst. Lett. 13(1): 25-28 (2021) - [j17]Ehsan Atoofian, Zayan Shaikh, Ali Jannesari:
Reducing Energy in GPGPUs through Approximate Trivial Bypassing. ACM Trans. Embed. Comput. Syst. 20(2): 13:1-13:27 (2021) - [j16]Jason Servais, Ehsan Atoofian:
Adaptive Computation Reuse for Energy-Efficient Training of Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 20(6): 114:1-114:24 (2021) - [c37]Ehsan Atoofian:
Sparsity-aware Power Gating for Tensor Cores. SBAC-PAD 2021: 94-103 - 2020
- [j15]Milad Mohammadi, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally:
Energy Efficient On-Demand Dynamic Branch Prediction Models. IEEE Trans. Computers 69(3): 453-465 (2020) - [j14]Ehsan Atoofian:
Approximate Cache in GPGPUs. ACM Trans. Embed. Comput. Syst. 19(5): 40:1-40:22 (2020) - [c36]Zayan Shaikh, Ehsan Atoofian:
Approximate trivial instructions. CF 2020: 1-9
2010 – 2019
- 2018
- [j13]Yang Xiao, Thireshan Jeyakumaran, Ehsan Atoofian, Ali Jannesari:
Improving performance of transactional memory through machine learning. Concurr. Comput. Pract. Exp. 30(10) (2018) - [j12]Ahmad Lashgar, Ehsan Atoofian, Amirali Baniasadi:
TELEPORT: Hardware/software alternative to CUDA shared memory programming. Microprocess. Microsystems 63: 169-181 (2018) - [j11]Ehsan Atoofian, Sean Rea:
Data-type specific cache compression in GPGPUs. J. Supercomput. 74(4): 1609-1635 (2018) - [c35]Sean Rea, Ehsan Atoofian:
Mitigating Critical Path Decompression Latency in Compressed L1 Data Caches Via Prefetching. IPDPS Workshops 2018: 694-701 - [c34]Ahmad Lashgar, Ehsan Atoofian, Amirali Baniasadi:
Loop Perforation in OpenACC. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 163-170 - 2017
- [j10]Ehsan Atoofian, Ahsan Saghir:
An efficient racetrack memory for L2 cache in GPGPUs. Comput. Syst. Sci. Eng. 32(6) (2017) - [j9]Ahsan Saghir, Ehsan Atoofian, Ali Manzak:
Reducing Power of Memory Hierarchy in General Purpose Graphics Processing Units. J. Low Power Electron. 13(2): 149-165 (2017) - 2016
- [c33]Ehsan Atoofian:
Compressed L1 data cache and L2 cache in GPGPUs. ASAP 2016: 1-8 - [c32]Thireshan Jeyakumaran, Ehsan Atoofian, Yang Xiao, Zhen Li, Ali Jannesari:
Improving Performance of Transactional Applications through Adaptive Transactional Memory. PDP 2016: 192-199 - [c31]Ehsan Atoofian:
A low power STT-RAM based register file for GPGPUs. SAC 2016: 1732-1738 - [c30]Ehsan Atoofian:
Temperature-Aware Register Mapping in GPGPUs. Trustcom/BigDataSE/ISPA 2016: 1636-1643 - [c29]Ehsan Atoofian:
Many-Thread Aware Compression in GPGPUs. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld 2016: 628-635 - 2015
- [j8]Amir Ghanbari Bavarsad, Ehsan Atoofian:
TurboLock: increasing associativity of lock table in transactional memory. Computing 97(6): 649-661 (2015) - [c28]Ehsan Atoofian:
Reducing shift penalty in Domain Wall Memory through register locality. CASES 2015: 177-186 - [c27]Yang Xiao, Zhen Li, Ehsan Atoofian, Ali Jannesari:
Automatic Optimization of Software Transactional Memory Through Linear Regression and Decision Tree. ICA3PP (4) 2015: 61-73 - [c26]Ehsan Atoofian, Ahsan Saghir:
Shift-aware racetrack memory. ICCD 2015: 427-430 - [c25]Ali Jannesari, Siegfried Benkner, Xinghui Zhao, Ehsan Atoofian, Yukinori Sato:
Workshop Preview of the 2nd International Workshop on Software for Parallel Systems (SEPS 2015). SPLASH (Companion Volume) 2015: 95-96 - [e1]Ali Jannesari, Siegfried Benkner, Xinghui Zhao, Ehsan Atoofian, Yukinori Sato:
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, SEPS@SPLASH 2015, Pittsburgh, PA, USA, October 27, 2015. ACM 2015, ISBN 978-1-4503-3910-0 [contents] - 2014
- [j7]Ehsan Atoofian:
Boosting performance of transactional memory through O-GEHL predictors. Microprocess. Microsystems 38(4): 254-262 (2014) - [c24]KuangLun Chen, Ehsan Atoofian, Ali Manzak:
Improving Power of Cache and Register File through Critical Path Instructions. DSD 2014: 349-355 - [c23]Ehsan Atoofian, Ali Manzak:
Power-Aware L1 and L2 Caches for GPGPUs. Euro-Par 2014: 354-365 - [c22]Ehsan Atoofian:
Reducing Static and Dynamic Power of L1 Data Caches in GPGPUs. IPDPS Workshops 2014: 798-804 - [c21]Ehsan Atoofian:
Acceleration of Software Transactional Memory through Hardware Clock. MES 2014: 41-47 - 2013
- [j6]Ehsan Atoofian, Amirali Baniasadi, Yvonne Coady:
ARV-ALA: Improving performance of software transactional memory through adaptive read and write policies. Sci. Comput. Program. 78(9): 1559-1571 (2013) - [j5]Ehsan Atoofian:
Improving performance of software transactional memory through contention locality. J. Supercomput. 64(2): 527-547 (2013) - [c20]Ehsan Atoofian:
VGTS: Variable Granularity Transactional Snoop. Euro-Par 2013: 203-214 - [c19]Amir Ghanbari Bavarsad, Ehsan Atoofian:
Read-Write Lock Allocation in Software Transactional Memory. ICPP 2013: 680-687 - [c18]Ehsan Atoofian:
Consistency Check through O-GEHL Predictors. PDP 2013: 218-224 - [c17]Ehsan Atoofian:
TxSnoop: Power-Aware Transactional Snoop. TrustCom/ISPA/IUCC 2013: 935-940 - 2012
- [c16]Ehsan Atoofian, Amir Ghanbari Bavarsad:
Speculative Versioning through Perceptron Predictors. HPCC-ICESS 2012: 1125-1130 - [c15]Ehsan Atoofian, Amir Ghanbari Bavarsad:
Maintaining Consistency in Software Transactional Memory through Dynamic Versioning Tuning. ICA3PP (2) 2012: 40-49 - [c14]Amir Ghanbari Bavarsad, Ehsan Atoofian:
TRT: Transactional Read Tracking. PDCAT 2012: 614-617 - [c13]Ehsan Atoofian:
ArTA: Adaptive Granularity in Transactional Applications. PDP 2012: 74-80 - [c12]Ehsan Atoofian, Amir Ghanbari Bavarsad:
AGC: adaptive global clock in software transactional memory. PMAM 2012: 11-16 - 2011
- [c11]Ehsan Atoofian:
Speculative Contention Avoidance in Software Transactional Memory. IPDPS Workshops 2011: 1417-1423
2000 – 2009
- 2008
- [j4]Ehsan Atoofian, Amirali Baniasadi:
Using supplier locality in power-aware interconnects and caches in chip multiprocessors. J. Syst. Archit. 54(5): 507-518 (2008) - [c10]Ehsan Atoofian, Amirali Baniasadi, Yvonne Coady:
Adaptive Read Validation in Time-Based Software Transactional Memory. Euro-Par Workshops 2008: 152-162 - [c9]Ehsan Atoofian, Amirali Baniasadi:
Exploiting program cyclic behavior to reduce memory latency in embedded processors. SAC 2008: 1482-1486 - 2007
- [j3]Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai:
Exploiting Speculation Cost Prediction in Power-Aware Applications. J. Low Power Electron. 3(1): 43-53 (2007) - [j2]Ehsan Atoofian, Amirali Baniasadi:
Speculative trivialization point advancing in high-performance processors. J. Syst. Archit. 53(9): 587-601 (2007) - [c8]Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian:
Computational and storage power optimizations for the O-GEHL branch predictor. Conf. Computing Frontiers 2007: 105-112 - [c7]Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai:
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. Conf. Computing Frontiers 2007: 259-266 - [c6]Ehsan Atoofian, Amirali Baniasadi:
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors. IPDPS 2007: 1-8 - 2006
- [j1]Ehsan Atoofian, Zainalabedin Navabi:
A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. 21(1): 141-146 (2006) - 2005
- [c5]Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail:
Low-power prediction based data transfer architecture. CICC 2005: 313-316 - [c4]Ehsan Atoofian, Amirali Baniasadi:
Improving Energy-Efficiency by Bypassing Trivial Computations. IPDPS 2005 - [c3]Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha:
A low-power scan-path architecture. ISCAS (5) 2005: 5278-5281 - 2003
- [c2]Ehsan Atoofian, Zainalabedin Navabi:
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium 2003: 84-89 - [c1]Ehsan Atoofian, Zainalabedin Navabi:
A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397
Coauthor Index
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last updated on 2024-11-20 21:58 CET by the dblp team
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