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2020 – today
- 2024
[c7]Kento Mishima, Naoya Niwa
, Kazutoshi Wakabayashi, Hiroe Iwasaki:
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. COOL CHIPS 2024: 1-3- 2023
- [j2]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106(2): 170-180 (2023) - 2022
- [j1]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. 105-D(12): 2057-2065 (2022) - [c6]Zhou Yuqing, Naoya Niwa, Hideharu Amano:
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network. MCSoC 2022: 361-367 - 2021
- [c5]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR 2021: 56-64 - [c4]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP 2021: 134-142
2010 – 2019
- 2019
- [c3]Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c2]Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa:
The Case for Water-Immersion Computer Boards. ICPP 2019: 29:1-29:10 - 2018
- [c1]Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185
Coauthor Index
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