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ORCIDRoberto Nonis
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2020 – today
- 2023
[j14]Alessio Cortiula
, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 940-951 (2023)- [j13]Giuseppe E. Biccario, Oleg Vitrenko, Roberto Nonis, Stefano D'Amico:
A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 636-643 (2023) - 2021
- [j12]Giuseppe E. Biccario, Oleg Vitrenko, Roberto Nonis, Stefano D'Amico:
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4626-4635 (2021) - [j11]Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis:
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1392-1401 (2021) - 2020
- [j10]Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1369-1373 (2020) - [c19]Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis:
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c18]Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. APCCAS 2019: 225-228 - [c17]Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua:
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. ESSCIRC 2019: 45-48 - [c16]Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin, Marco Scapol, Andrea Bandiziol, Andrea Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. MIPRO 2019: 112-116 - 2018
- [j9]Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Roberto Nonis, Carlo Samori, Salvatore Levantino:
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits 53(12): 3565-3575 (2018) - [j8]Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino:
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 914-924 (2018) - [j7]Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua:
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 657-661 (2018) - [j6]Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri:
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1305-1309 (2018) - [c15]Andrea Donno, Stefano D'Amico, Roberto Nonis, Peter Thurner:
Low noise active loop filter for radar PLL applications. ICICDT 2018: 77-80 - [c14]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri:
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. ISCAS 2018: 1-5 - [c13]Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino:
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC 2018: 248-250 - [c12]Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony:
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. ISSCC 2018: 388-389 - 2017
- [c11]Dmytro Chemiak, Salvatore Levantino, Carlo Samori, Roberto Nonis:
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. ISCAS 2017: 1-4 - [c10]Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - 2016
- [c9]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. APCCAS 2016: 321-324 - [c8]Werner Grollitsch, Roberto Nonis:
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. ESSCIRC 2016: 201-204 - [c7]Jaeha Kim, Roberto Nonis:
Session 10 overview: Advanced wireline transceivers and PLLs. ISSCC 2016: 180-181 - [c6]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a transmitter for high-speed serial interfaces in automotive micro-controller. MIPRO 2016: 84-88 - 2015
- [c5]Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt:
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. ESSCIRC 2015: 392-395 - [c4]Andrea Cossettini, Andrea Cristofoli, Werner Grollitsch, Lino Alves, Roberto Nonis, Luca Della Ricca, Pierpaolo Palestri, Luca Selmi:
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. RTSI 2015: 34-38 - 2013
- [j5]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits 48(12): 3134-3145 (2013) - [c3]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC 2013: 356-357 - 2010
- [j4]Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni, Luca Selmi:
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. Int. J. Circuit Theory Appl. 38(6): 607-629 (2010) - [c2]Werner Grollitsch, Roberto Nonis, Nicola Da Dalt:
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC 2010: 478-479
2000 – 2009
- 2008
- [j3]Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi:
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1628-1638 (2008) - 2007
- [b1]Roberto Nonis:
Modeling and design of low power integrated circuits for frequency synthesis in CMOS technology. University of Udine, Italy, 2007 - [j2]Roberto Nonis, Enzo Palumbo, Pierpaolo Palestri, Luca Selmi:
A Design Methodology for MOS Current-Mode Logic Frequency Dividers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 245-254 (2007) - 2005
- [j1]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. IEEE J. Solid State Circuits 40(6): 1303-1309 (2005) - 2004
- [c1]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture. ISCAS (4) 2004: 553-556
Coauthor Index
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