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ORCIDKimia Zamiri Azar
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2020 – today
- 2024
[j11]Md Sami Ul Islam Sami
, Tao Zhang, Amit Mazumder Shuvo, Md. Saad Ul Haque, Paul Calzada, Kimia Zamiri Azar, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration. IEEE Access 12: 48081-48107 (2024)- [j10]Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
Fuzzing for Automated SoC Security Verification: Challenges and Solution. IEEE Des. Test 41(4): 7-16 (2024) - [j9]Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi:
Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions. IEEE Des. Test 41(4): 26-34 (2024) - [j8]Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi:
The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3068-3082 (2024) - [j7]Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration. IEEE Trans. Inf. Forensics Secur. 19: 2771-2785 (2024) - [j6]Paul Calzada, Md Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM. ACM Trans. Design Autom. Electr. Syst. 29(1): 9:1-9:25 (2024) - [j5]Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi:
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 305-318 (2024) - [c25]Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection. ASPDAC 2024: 355-361 - [c24]Galib Ibne Haidar, Kimia Zamiri Azar, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi:
GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package. DAC 2024: 299:1-299:6 - [c23]Nurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation. DATE 2024: 1-6 - [c22]Bulbul Ahmed, M. Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation. ACM Great Lakes Symposium on VLSI 2024: 489-494 - [c21]Paul Calzada, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration. ISVLSI 2024: 379-384 - [c20]Galib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi:
SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits. ITC 2024: 303-312 - 2023
- [c19]Hasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SHarPen: SoC Security Verification by Hardware Penetration Test. ASP-DAC 2023: 579-584 - [c18]Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing. DATE 2023: 1-6 - [c17]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
SheLL: Shrinking eFPGA Fabrics for Logic Locking. DATE 2023: 1-6 - [c16]Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi:
EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators. DFT 2023: 1-6 - [c15]Hasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy. DFT 2023: 1-6 - [c14]Upoma Das, M. Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi:
PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates. ETS 2023: 1-6 - [c13]Mohammad Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Hadi Mardani Kamali:
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking. ACM Great Lakes Symposium on VLSI 2023: 685-690 - [c12]Muhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing. ICCAD 2023: 1-9 - 2022
- [c11]Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers. HOST 2022: 13-16 - [i11]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
Advances in Logic Locking: Past, Present, and Prospects. IACR Cryptol. ePrint Arch. 2022: 260 (2022) - [i10]Kimia Zamiri Azar, Muhammad Monir Hossain, Arash Vafaei, Hasan Al Shaikh, Nurun N. Mondol, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi:
Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions. IACR Cryptol. ePrint Arch. 2022: 394 (2022) - 2021
- [j4]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains. IEEE Access 9: 73133-73151 (2021) - [j3]Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan:
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 643-656 (2021) - [c10]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing. ISQED 2021: 387-394 - 2020
- [c9]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. ACM Great Lakes Symposium on VLSI 2020: 217-222 - [c8]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
InterLock: An Intercorrelated Logic and Routing Locking. ICCAD 2020: 78:1-78:9 - [c7]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. ICCAD 2020: 79:1-79:9 - [c6]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. ISVLSI 2020: 153-159 - [c5]Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan:
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. VTS 2020: 1-6 - [i9]Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan:
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. CoRR abs/2002.07857 (2020) - [i8]Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Avesta Sasan:
ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things. CoRR abs/2004.06235 (2020) - [i7]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. CoRR abs/2005.04262 (2020) - [i6]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. CoRR abs/2005.11789 (2020) - [i5]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
InterLock: An Intercorrelated Logic and Routing Locking. CoRR abs/2009.02206 (2020) - [i4]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. CoRR abs/2009.02208 (2020)
2010 – 2019
- 2019
- [j2]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(1): 97-122 (2019) - [c4]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. DAC 2019: 89 - [c3]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
Threats on Logic Locking: A Decade Later. ACM Great Lakes Symposium on VLSI 2019: 471-476 - [c2]Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan:
COMA: Communication and Obfuscation Management Architecture. RAID 2019: 181-195 - [i3]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
Threats on Logic Locking: A Decade Later. CoRR abs/1905.05896 (2019) - [i2]Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan:
COMA: Communication and Obfuscation Management Architecture. CoRR abs/1909.00493 (2019) - 2018
- [j1]Hadi Mardani Kamali, Kimia Zamiri Azar, Shaahin Hessabi:
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture. IEEE Trans. Computers 67(2): 208-221 (2018) - [c1]Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan:
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. ISVLSI 2018: 405-410 - [i1]Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan:
LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. CoRR abs/1804.11275 (2018)
Coauthor Index
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