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2020 – today
- 2024
[i1]Fabien Geyer, Johannes Freitag, Tobias Schulz, Sascha Uhrig:
Efficient and Mathematically Robust Operations for Certified Neural Networks Inference. CoRR abs/2401.08225 (2024)
2010 – 2019
- 2019
- [j10]Daniel Schneider
, Jens Braband, Erwin Schoitsch, Sascha Uhrig, Stefan Katzenbeisser:
Safety and Security Coengineering in Embedded Systems. Secur. Commun. Networks 2019: 5381856:1-5381856:2 (2019) - [e1]Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings. Lecture Notes in Computer Science 11479, Springer 2019, ISBN 978-3-030-18655-5 [contents] - 2018
- [c43]Johannes Freitag, Sascha Uhrig:
Closed Loop Controller for Multicore Real-Time Systems. ARCS 2018: 45-56 - [c42]Johannes Freitag, Sascha Uhrig, Theo Ungerer:
Virtual Timing Isolation for Mixed-Criticality Systems. ECRTS 2018: 13:1-13:23 - 2017
- [c41]Ankit Agrawal, Gerhard Fohler, Johannes Freitag, Jan Nowotsch, Sascha Uhrig, Michael Paulitsch:
Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. ECRTS 2017: 2:1-2:22 - [c40]Alessandra Melani, Renato Mancuso, Marco Caccamo, Giorgio C. Buttazzo, Johannes Freitag, Sascha Uhrig:
A scheduling framework for handling integrated modular avionic systems on multicore platforms. RTCSA 2017: 1-10 - 2016
- [j9]Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka:
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. 15(3): 53:1-53:27 (2016) - [c39]Werner Weber, Alfred Hoess, Jan van Deventer, Frank Oppenheimer, Rolf Ernst, Adam Kostrzewa, Philippe Dore, Thierry Goubier, Haris Isakovic, Norbert Druml, Egon Wuchner, Daniel Schneider, Erwin Schoitsch, Eric Armengaud, Thomas Soderqvist, Massimo Traversone, Sascha Uhrig, Juan-Carlos Perez-Cortes, Sergio Sáez, Juha Kuusela, Mark van Helvoort, Xing Cai, Bjørn Nordmoen, Geir Yngve Paulsen, Hans Petter Dahle, Michael Geissel, Jürgen Salecker, Peter Tummeltshammer:
The EMC2 Project on Embedded Microcontrollers: Technical Progress after Two Years. DSD 2016: 524-531 - [c38]Ankit Agrawal, Gerhard Fohler, Jan Nowotsch, Sascha Uhrig, Michael Paulitsch:
Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. RTAS 2016: 53 - 2015
- [c37]Sascha Uhrig, Lillian Tadros, Arthur Pyka:
MESI-Based Cache Coherence for Hard Real-Time Multicore Systems. ARCS 2015: 212-223 - [c36]Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin:
The shift to multicores in real-time and safety-critical systems. CODES+ISSS 2015: 220-229 - [c35]Arthur Pyka, Pavel G. Zaykov, Hugues Cassé, Haluk Ozaktas, Christine Rochange, Sascha Uhrig:
Case study: Performance and WCET analysis for parallelised avionic applications with ODC2. INDIN 2015: 1400-1407 - 2014
- [b2]Christine Rochange, Sascha Uhrig, Pascal Sainrat:
Time-Predictable Architectures. FOCUS - Computer Engineering Series, iSTE / Wiley 2014, ISBN 978-1-84821-593-1, pp. I-VIII, 1-180 - [j8]Arthur Pyka, Mathias Rohde, Sascha Uhrig:
A real-time capable coherent data cache for multicores. Concurr. Comput. Pract. Exp. 26(6): 1342-1354 (2014) - [c34]Arthur Pyka, Mathias Rohde, Sascha Uhrig:
Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems. ICSAMOS 2014: 107-114 - 2013
- [j7]Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla:
A hard real-time capable multi-core SMT processor. ACM Trans. Embed. Comput. Syst. 12(3): 79:1-79:26 (2013) - [c33]Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka:
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. DSD 2013: 363-370 - [c32]Arthur Pyka, Mathias Rohde, Sascha Uhrig:
Performance Evaluation of the Time Analysable On-Demand Coherent Cache. TrustCom/ISPA/IUCC 2013: 1887-1892 - 2012
- [j6]Sascha Uhrig, Ralf Jahr, Theo Ungerer:
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor. IET Comput. Digit. Tech. 6(5): 334-341 (2012) - [c31]Sascha Uhrig:
Implementing a ring-based real-time capable network using a multithreaded Java processor. JTRES 2012: 185-192 - [c30]Julian Wolf, Bernhard Fechner, Sascha Uhrig, Theo Ungerer:
Fine-grained timing and control flow error checking for hard real-time task execution. SIES 2012: 257-266 - 2011
- [j5]Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer:
RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor. Comput. Syst. Sci. Eng. 26(6) (2011) - [c29]Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer:
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware. ARCS 2011: 122-134 - [c28]Sascha Uhrig:
Tracing Static Fields of Embedded Parallel Java Applications. COMPSAC Workshops 2011: 516-519 - [c27]Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Julian Wolf, Theo Ungerer, Sascha Uhrig, Zlatko Petrov:
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. ISORC 2011: 233-240 - 2010
- [j4]Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische:
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro 30(5): 66-75 (2010) - [c26]Florian Kluge, Sascha Uhrig, Jörg Mische, Benjamin Satzger, Theo Ungerer:
Dynamic Workload Prediction for Soft Real-Time Applications. CIT 2010: 1841-1848 - [c25]Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer:
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. ARCS 2010: 2-14 - [c24]Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer:
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. DSD 2010: 71-79 - [c23]Ralf Jahr, Basher Shehan, Sascha Uhrig, Theo Ungerer:
Static Speculation as Post-link Optimization for the Grid Alu Processor. Euro-Par Workshops 2010: 145-152 - [c22]Sascha Uhrig:
The MANy JAva Core processor (MANJAC). HPCS 2010: 188 - [c21]Florian Kluge, Sascha Uhrig, Jörg Mische, Benjamin Satzger, Theo Ungerer:
Optimisation of Energy Consumption of Soft Real-Time Applications by Workload Prediction. ISORC Workshops 2010: 63-72 - [c20]Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer:
RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor. ISORC 2010: 193-201 - [c19]Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig:
The embedded Java benchmark suite JemBench. JTRES 2010: 120-127 - [c18]Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
Using SMT to Hide Context Switch Times of Large Real-Time Tasksets. RTCSA 2010: 255-264
2000 – 2009
- 2009
- [c17]Sascha Uhrig, Theo Ungerer:
A Garbage Collection Technique for Embedded Multithreaded Multicore Processors. ARCS 2009: 207-218 - [c16]Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. HiPEAC 2009: 125-139 - [c15]Sascha Uhrig:
Risks and chances of many-core processors. HPCS 2009: 80 - [c14]Sascha Uhrig:
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. SAMOS 2009: 68-77 - [c13]Florian Kluge, Chenglong Yu, Jörg Mische, Sascha Uhrig, Theo Ungerer:
Implementing AUTOSAR scheduling and resource management on an embedded SMT processor. SCOPES 2009: 33-42 - 2008
- [j3]Sascha Uhrig:
A Flexible Java-on-Chip Solution (Eine flexible Java-on-Chip Lösung). it Inf. Technol. 50(5): 317-323 (2008) - [c12]Florian Kluge, Jörg Mische, Sascha Uhrig, Theo Ungerer:
An Operating System Architecture for Organic Computing in Embedded Real-Time Systems. ATC 2008: 343-357 - [c11]Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
Exploiting spare resources of in-order SMT processors executing hard real-time threads. ICCD 2008: 371-376 - [c10]Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer:
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. MEDEA@PACT 2008: 38-45 - [c9]Florian Kluge, Sascha Uhrig, Jörg Mische, Theo Ungerer:
A Two-Layered Management Architecture for Building Adaptive Real-Time Systems. SEUS 2008: 126-137 - 2007
- [c8]Sascha Uhrig, Jörg Wiese:
jamuth: an IP processor core for embedded Java real-time systems. JTRES 2007: 230-237 - [c7]Sascha Uhrig, Jörg Mische, Theo Ungerer:
An IP Core for Embedded Java Systems. SAMOS 2007: 263-272 - 2006
- [c6]Sascha Uhrig, Stefan Maier, Georgi Kuzmanov, Theo Ungerer:
Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. IPDPS 2006 - 2005
- [j2]Uwe Brinkschulte, Sascha Uhrig, Theo Ungerer:
Der mehrfädige Komodo-Mikrocontroller (The Multithreaded Komodo Microcontroller). it Inf. Technol. 47(3): 117-122 (2005) - [c5]Sascha Uhrig, Theo Ungerer:
Energy Management for Embedded Multithreaded Processors with Integrated EDF Scheduling. ARCS 2005: 1-17 - 2004
- [b1]Sascha Uhrig:
Optimierung des Energieverbrauchs in echtzeitfähigen, mehrfädigen Prozessoren. University of Augsburg, 2004, ISBN 3-8325-0538-5, pp. 1-157 - [c4]Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer:
CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) 2004: 616-620 - [c3]Sascha Uhrig, Theo Ungerer:
Fine-grained power management for multithreaded processor cores. SAC 2004: 907-908 - 2003
- [j1]Jochen Kreuzinger, Uwe Brinkschulte, Matthias Pfeffer, Sascha Uhrig, Theo Ungerer:
Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocess. Microsystems 27(1): 19-31 (2003) - [c2]Sascha Uhrig, Theo Ungerer:
Hardware-based Power Management for Real-Time Applications. ISPDC 2003: 258-265 - 2002
- [c1]Matthias Pfeffer, Sascha Uhrig, Theo Ungerer, Uwe Brinkschulte:
A Real-Time Java System on a Multithreaded Java Microcontroller. Symposium on Object-Oriented Real-Time Distributed Computing 2002: 34-44
Coauthor Index
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last updated on 2024-05-08 21:51 CEST by the dblp team
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