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ORCIDShaolan Li
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2020 – today
- 2024
[j18]Yan Lu
, Shaolan Li:
Guest Editorial 2023 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 59(3): 651-652 (2024)- [c25]Tian Xie, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong Suk Kang, Shaolan Li:
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping. CICC 2024: 1-2 - 2023
- [c24]Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu:
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. BioCAS 2023: 1-5 - [c23]Xitie Zhang, Evren F. Arkan, Coskun Tekes, Tzuhan Wang, F. Levent Degertekin, Shaolan Li:
A 1.11 mm2 Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming. ESSCIRC 2023: 309-312 - [c22]Dayou Wu, Guochao Peng, Yiwan Ai, Huan Li, Shaolan Li, Yating Peng:
A Systematic and Innovative Six-in-One Evaluation Framework to Drive the Development of Future Hidden Champions. HCI (26) 2023: 138-155 - 2022
- [j17]Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu:
Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. 4(8) (2022) - [j16]Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li:
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. IEEE J. Solid State Circuits 57(12): 3804-3815 (2022) - [j15]Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun:
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2249-2262 (2022) - [j14]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 784-788 (2022) - [c21]Tzuhan Wang, Tian Xie, Zhe Liu, Shaolan Li:
An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. ISSCC 2022: 418-420 - 2021
- [j13]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j12]Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li:
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. IEEE J. Solid State Circuits 56(12): 3668-3680 (2021) - [c20]Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun:
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC 2021: 1-2 - [c19]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. IMW 2021: 1-4 - [c18]Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li:
27.3 A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation. ISSCC 2021: 374-376 - 2020
- [j11]Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun:
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits 55(2): 356-368 (2020) - [j10]Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j9]Shaolan Li, David Z. Pan, Nan Sun:
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits 55(5): 1337-1350 (2020) - [j8]Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun:
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j7]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun:
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [c17]Shaolan Li:
A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier. MWSCAS 2020: 758-761
2010 – 2019
- 2019
- [j6]Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun:
Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. 102-C(7): 509-519 (2019) - [j5]Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun:
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. IEEE J. Solid State Circuits 54(2): 428-440 (2019) - [j4]Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu:
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [j3]Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun:
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1342-1354 (2019) - [c16]Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC 2019: 1-4 - [c15]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c14]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c13]Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c12]Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8 - [c11]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - [c10]Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC 2019: 64-66 - [c9]Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun:
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC 2019: 296-297 - [c8]Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun:
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits 2019: 144- - 2018
- [j2]Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun:
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits 53(12): 3484-3496 (2018) - [c7]Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun:
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC 2018: 93-94 - [c6]Arindam Sanyal, Shaolan Li, Nan Sun:
Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. ISCAS 2018: 1-5 - [c5]Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun:
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. ISSCC 2018: 234-236 - [c4]Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun:
A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer. VLSI Circuits 2018: 201-202 - 2017
- [j1]Shaolan Li, Abhishek Mukherjee, Nan Sun:
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS. IEEE J. Solid State Circuits 52(7): 1940-1952 (2017) - [c3]Biying Xu, Shaolan Li, Nan Sun, David Z. Pan:
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC 2017: 12:1-12:6 - [c2]Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan:
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD 2017: 55-62 - 2016
- [c1]Shaolan Li, Nan Sun:
A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. ESSCIRC 2016: 241-244
Coauthor Index
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last updated on 2024-08-05 21:12 CEST by the dblp team
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