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2020 – today
- 2024
[j2]Eric Guthmuller
, César Fuguet, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand:
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation. IEEE Trans. Computers 73(7): 1683-1697 (2024)- [c11]Davy Million, Noelia Oliete-Escuín, César Fuguet:
Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache. DATE 2024: 1-2 - 2023
- [c10]César Fuguet Tortolero:
HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores. CF 2023: 377-378 - 2022
- [c9]Yves Durand, Eric Guthmuller, César Fuguet Tortolero, Jérôme Fereyre, Andrea Bocco, Riccardo Alidori:
Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor. ARITH 2022: 51-57 - 2021
- [j1]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021) - [c8]Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE 2021: 1-6 - 2020
- [c7]Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet Tortolero, Pierre Tissier, Benoît Charbonnier, Stéphane Malhouitre, Damien Saint-Patrice, Myriam Assous, Aditya Narayan, Ayse K. Coskun, Denis Dutoit, Pascal Vivet:
POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. DATE 2020: 1456-1461 - [c6]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2019
- [c5]Aditya Narayan, Yvain Thonnart, Pascal Vivet, César Fuguet Tortolero, Ayse K. Coskun:
WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs. DATE 2019: 516-521 - 2018
- [c4]Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet:
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - 2017
- [c3]Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot:
A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols. ARCS 2017: 111-123 - [c2]Yves Durand, Christian Bernard, Romain Lemaire, César Fuguet Tortolero, Emilie Garat:
A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems. DSD 2017: 192-197 - [c1]Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot:
Trace-driven exploration of sharing set management strategies for cache coherence in manycores. NEWCAS 2017: 77-80 - 2015
- [b1]César Fuguet Tortolero:
Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente). Pierre and Marie Curie University, Paris, France, 2015
Coauthor Index
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